 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| cypress semiconductor corporation 198 champion court san jose , ca 95134 - 1709 408 - 943 - 2600 document number: 002 - 14921 rev. ** revised july 1, 2 016 the following document contains information on cypress products. although the document is marked with the name broadcom , the company that originally developed the specification, cypress will continue to offer these pr oducts to new and existing customers. continuity of specifications there is no change to this document as a result of offering the device as a cypress product. any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. future revisions will occur when appropriate, and changes will be noted in a document history page. continuity of ordering part numbers cypress continues to support existing part numbers. to order these products , please use only the ordering part numbers listed in this document. for more information please visit our website at www .cypress.com or contact your local sales office for additional information about cypress pro ducts and services. our customers cypress is for true innovators C in companies both large and small. our customers are smart, aggressive, out - of - the - box thinkers who design and develop game - changing products that revolutionize their industries or create n ew industries with products and solutions that nobody ever thought of before. about cypress founded in 1982, cypress is the leader in advanced embedded system solutions for the worlds most innovative automotive, industrial, home automation and appliances, consumer electronics and medical products. cypresss programmable systems - on - chip, general - purpose microcontrollers, analog ics, wireless and usb - based connectivity solutions and reliable, high - performance memories help engineers design differentiated pro ducts and get them to market first. cypress is committed to providing customers with the best support and engineering resources on the planet enabling innovators and out - of - the - box thinkers to disrupt markets and create new product categories in record tim e. to learn more, go to www.cypress.com .
43243-ds100-r 5300 california avenue ? irvine, ca 92617 ? phone: 949-926-5000 ? fax: 949-926-5203 april 16, 2015 preliminary data sheet bcm43243 single-chip ieee 802.11 a/b/g/n 22 mac/baseband/radio figure 1: functional block diagram general description general description the broadcom ? bcm43243 is a single-chip device for wireless media systems. it integrates a mac, baseband, and radio that support ieee 802.11 a/b/g and 22 ieee 802.11n, and uses usb 2.0 as the wlan host interface. the bcm43243 takes advantage of the high throughput and extended range of the broadcom second-generation mimo solution. with mimo, the information is sent and received over two or more antennas simultaneously using the same frequency band, providing greater range and higher throughput, while maintaining compatibility with legacy ieee 802.11a/b/g devices. this is accomplished through a combination of enhanced mac and phy implementations, including spatial multiplexing modes in the transmitter and receiver and advanced digital signal processing techniques that improve receive sensitivity. the bcm43243 architecture, with its fully integrated dual-band radio transceiver, supports 2 2 antennas. it also supports 20 mhz and 40 mhz channels, allowing for phy layer throughput up to 300 mbps. using advanced design techniques and process technology to reduce active and standby power, the bcm43243 is designed to address the needs of media-embedded applications that require minimal power consumption and compact size. the bcm43243 includes a power management unit (pmu) that simplifies the system power topology and allows for direct operation with a 3.3v or 5v supply, which provides flexibility. the bcm43243 includes power saving schemes such as single-core listen (ocl), single-core demodulation of siso/stbc packets, and dynamic maximum likelihood (ml) demapping (which is based on channel conditions). wlan host i/f 5g wlan 2g wlan ant1 usb 2.0 5g wlan 2g wlan diplexer ant0 diplexer 5 ghz fem 2.4 ghz fem 5 ghz fem 2.4 ghz fem bcm43243 revision history bcm43243 preliminary data sheet broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 2 broadcom confidential features features ieee 802.11x features ? single-band 2.4 ghz ieee 802.11 b/g/n or dual-band 2.4 ghz and 5 ghz ieee 802.11 a/b/g/n. ? hardware support for virtual simultaneous dual-band operation with switching times less than 1 ms. ? dual-stream ieee 802.11n support for 20 mhz and 40 mhz channels provides phy layer rates up to 300 mbps for typical upper- layer throughput up to 200 mbps. ? ieee 802.11n stbc (space-time block coding) in both tx and rx for improved range and power efficiency. ? integrated 2.4 ghz and 5 ghz power amplifiers as well as six rf control signals to control external rf switches or lnas. ? internal fractional npll allows support for a wide range of reference clock frequencies. ? standard high-speed usb 2.0 host interface. ? integrated arm ? cortex-m3 ? processor and on-chip memory for complete wlan subsystem functionality, minimizing the need to wake up the applications processor (ap) for standard wlan functions. (this allows for further minimization of power consumption, while maintaining the ability to field-upgrade with future features. on-chip memory includes 544 kb sram and 640 kb rom.) ? onedriver ? software architecture for easy migration from existing embedded wlan devices as well as future devices. ? advanced power topology allows for very low active and standby power. general features ? programmable dynamic power management. ? 3072-bit otp for storing board parameters. ? 16 general-purpose i/os (gpios). ? fcfbga package (10 mm 10 mm, 0.4 mm pitch) allows low-cost 4-layer pcb design with no hidden vias. security ?wpa ? and wpa2 ? (personal) support for powerful encryption and authentication. ? aes and tkip in hardware for faster data encryption and ieee 802.11i compatibility. ? reference wlan subsystem provides cisco ? compatible extensions (ccx, ccx 2.0, ccx 3.0, ccx 4.0, ccx 5.0). ? reference wlan subsystem provides wi-fi protected setup (wps). ? worldwide regulatory support. broadcom corporation 5300 california avenue irvine, ca 92617 ? 2015 by broadcom corporation all rights reserved printed in the u.s.a. broadcom ? , the pulse logo, connecting everything ? , the connecting everything logo, and onedriver ? are among the trademarks of broadcom corporation and/or its affiliates in the united states, certain other countries and/or the eu. any other trademarks or trade names mentioned are the property of their respective owners. this data sheet (including, without limitation, the broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high-risk application. broadcom provides this data sheet ?as-is,? without warranty of any kind. broadcom disclaims all warranties, expressed and implied, including, without limitation, the implied warranties of merchantability, fitnes s for a particular purpose, and non- infringement. revision history revision date change description 43243-ds100-r 04/16/15 initial release table of contents bcm43243 preliminary data sheet broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 4 broadcom confidential table of contents about this document ............................................................................................................................... ... 9 purpose and audience ........................................................................................................... ................. 9 acronyms and abbreviations..................................................................................................... .............. 9 document conventions ........................................................................................................... ................ 9 technical support ............................................................................................................................... ......... 9 section 1: overview .......................................................................................................... 10 overview ............................................................................................................................... ....................... 10 features ............................................................................................................................... ........................ 11 standards compliance ............................................................................................................................... 11 section 2: power supplies and power management ..................................................... 13 power supply topology ............................................................................................................................. 13 bcm43243 pmu features .......................................................................................................... .......... 13 wlan power management ........................................................................................................................ 15 pmu sequencing ............................................................................................................................... ......... 15 power-up/power-down/reset circuits ..................................................................................................... 16 section 3: frequency references.................................................................................... 17 crystal interface and clock generation ................................................................................................... 17 tcxo ............................................................................................................................... ............................. 18 section 4: wlan global functions ................................................................................. 20 wlan cpu and memory subsystem ........................................................................................................ 20 one-time programmable memory ............................................................................................................ 20 gpio interface ............................................................................................................................... .............. 21 uart interface ............................................................................................................................... ............. 21 jtag interface ............................................................................................................................... ............. 21 section 5: usb interface................................................................................................... 22 wlan usb 2.0 interface ............................................................................................................................ 22 section 6: wireless lan mac and phy .......................................................................... 24 mac features ............................................................................................................................... .............. 24 mac description ................................................................................................................ ................... 24 psm ............................................................................................................................ ................... 25 wep ............................................................................................................................ ................... 26 txe ............................................................................................................................ .................... 26 rxe............................................................................................................................ .................... 26 ifs............................................................................................................................ ...................... 27 tsf ............................................................................................................................ .................... 27 table of contents bcm43243 preliminary data sheet broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 5 broadcom confidential nav............................................................................................................................ .................... 27 mac-phy interface.............................................................................................................. .......... 27 wlan phy description .............................................................................................................................. 2 8 phy features................................................................................................................... ..................... 28 section 7: wlan radio subsystem ............................................................................... 31 receiver path ............................................................................................................................... ............... 31 transmit path ............................................................................................................................... ............... 31 calibration ............................................................................................................................... .................... 31 section 8: pinouts and signal descriptions ................................................................... 33 ball map ............................................................................................................................... ........................ 33 pin list?ordered by pin number ............................................................................................................ 37 pin list?listed alphabetically by pin name ......................................................................................... 41 signal descriptions ............................................................................................................................... ..... 45 wlan gpio signals and strapping options ........................................................................................ 49 i/o states ............................................................................................................................... ...................... 50 section 9: dc characteristics .......................................................................................... 52 absolute maximum ratings ...................................................................................................................... 52 environmental ratings .............................................................................................................................. 5 3 electrostatic discharge specifications .................................................................................................... 53 recommended operating conditions and dc characteristics ............................................................. 54 section 10: wlan rf specifications .............................................................................. 55 introduction ............................................................................................................................... .................. 55 2.4 ghz band general rf specifications ................................................................................................. 56 wlan 2.4 ghz receiver performance specifications ............................................................................ 56 wlan 2.4 ghz transmitter performance specifications ....................................................................... 59 wlan 5 ghz receiver performance specifications ............................................................................... 60 wlan 5 ghz transmitter performance specifications .......................................................................... 63 general spurious emissions specifications ........................................................................................... 64 section 11: internal regulator electrical specifications ............................................... 65 core buck switching regulator ................................................................................................................ 65 cldo ............................................................................................................................... ............................ 67 lnldo1 ............................................................................................................................... ........................ 68 lnldo2 ............................................................................................................................... ........................ 69 section 12: system power consumption........................................................................ 70 wlan current consumption ..................................................................................................................... 70 section 13: interface timing and ac characteristics .................................................... 72 jtag timing ............................................................................................................................... ................ 72 table of contents bcm43243 preliminary data sheet broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 6 broadcom confidential section 14: power-up sequence and timing ................................................................. 73 sequencing of reset and regulator control signals ............................................................................. 73 control signal and timing ...................................................................................................... ............... 73 section 15: package information ..................................................................................... 74 package thermal characteristics ............................................................................................................. 74 junction temperature estimation and psi jt versus theta jc ............................................................. 74 environmental characteristics .................................................................................................................. 74 section 16: mechanical information ................................................................................ 75 section 17: ordering information .................................................................................... 76 list of figures bcm43243 preliminary data sheet broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 7 broadcom confidential list of figures figure 1: functional block diagram.............................................................................................. ..................... 1 figure 2: bcm43243 block diagram ................................................................................................ ............... 10 figure 3: typical power topology ................................................................................................ ................... 14 figure 4: recommended oscillator configuration .................................................................................. ......... 17 figure 5: recommended circuit to use with an external dedicated tcxo .................................................... 18 figure 6: recommended circuit to use with an external shared tcxo......................................................... 18 figure 7: wlan usb 2.0 host interface block diagram ............................................................................. .... 22 figure 8: wlan mac architecture ................................................................................................. ................. 25 figure 9: wlan phy block diagram................................................................................................ ............... 29 figure 10: stbc receive block diagram........................................................................................... ............. 30 figure 11: radio functional block diagram ....................................................................................... ............. 32 figure 12: fcfbga ball map, top view, 1 of 4?a1 through m12 ................................................................ 33 figure 13: fcfbga ball map, top view, 2 of 4?a13 through m23 .............................................................. 34 figure 14: fcfbga ball map, top view, 3 of 4?n1 through ac12 .............................................................. 35 figure 15: fcfbga ball map, top view, 4 of 4?n13 through ac23 ............................................................ 36 figure 16: port locations....................................................................................................... .......................... 55 figure 17: wlan = on ............................................................................................................ ........................ 73 figure 18: wlan = off ........................................................................................................... ....................... 73 figure 19: fcfbga package mechanical information ................................................................................ .... 75 list of tables bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 8 list of tables table 1: crystal oscillator and external clock ? requirements and performance.......................................... 19 table 2: pin list by pin number ................................................................................................. ..................... 37 table 3: alphabetical pin list by pin name...................................................................................... ............... 41 table 4: fcfbga signal descriptions............................................................................................. ................ 45 table 5: wlan gpio functions and strapping options .............................................................................. ... 49 table 6: i/o states ............................................................................................................. .............................. 50 table 7: absolute maximum ratings ............................................................................................... ................ 52 table 8: environmental ratings.................................................................................................. ..................... 53 table 9: esd specifications ..................................................................................................... ....................... 53 table 10: recommended operating conditions and dc characteristics ........................................................ 54 table 11: 2.4 ghz band general rf specifications................................................................................ ........ 56 table 12: wlan 2.4 ghz receiver performance specifications .................................................................... 56 table 13: wlan 2.4 ghz transmitter performance specifications ................................................................ 59 table 14: wlan 5 ghz receiver performance specifications ....................................................................... 6 0 table 15: wlan 5 ghz transmitter performance specifications ................................................................... 63 table 16: general spurious emissions specifications ............................................................................. ....... 64 table 17: core buck switching regulator (cbuck) specifications ................................................................ 65 table 18: cldo specifications ................................................................................................... ..................... 67 table 19: lnldo1 specifications ................................................................................................. ................... 68 table 20: lnldo2 specifications ................................................................................................. ................... 69 table 21: 2.4 ghz wlan current consumption ...................................................................................... ....... 70 table 22: 5 ghz wlan current consumption ........................................................................................ ........ 71 table 23: jtag timing characteristics ........................................................................................... ................ 72 table 24: package jedec thermal characteristics ................................................................................. ...... 74 broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 9 bcm43243 preliminary data sheet broadcom confidential about this document purpose and audience this data sheet provides details about the functional, operational, and electrical characteristics of the broadcom bcm43243. it is intended for hardware design, application, and oem engineers. acronyms and abbreviations in most cases, acronyms and abbreviations are defined on first use. for a comprehensive list of acronyms and other terms used in broadcom documents, go to: http://www.broadcom.com/press/glossary.php . document conventions the following conventions may be used in this document: technical support broadcom provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, pcb layout information, and software updates through its customer support portal ( https://support.broadcom.com ). for a csp account, contact your sales or engineering support representative. in addition, broadcom provides other product support through its downloads & support site ( http://www.broadcom.com/support/ ). convention description bold user input and actions: for example, type exit , click ok, press alt+c monospace code: #include command line commands and parameters: wl [-l] |
overview bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 10 section 1: overview overview the broadcom bcm43243 is a single-chip ieee 802.11 a/b/g and 2 2 ieee 802.11n device for wireless media systems that integrates the mac, baseband, and radio. bcm43243-based designs require few external components, provide size, form, and functional design flexibility, and can be produced in mass volumes at minimal cost. comprehensive power management circuitry and software ensure the system can meet the needs of media devices that require minimal power consumption and reliable operation. figure 2 shows the interconnect of all the major physical blocks in the bcm43243 and their associated external interfaces, which are described in greater detail in the following sections. figure 2: bcm43243 block diagram cortex m3 debug jtag sdp pmu ctrl xtal gpio uart jtag arm cm3 power supply usb jtag sd io g spi usb wlan eci 2.4 ghz wlan fem lna diplexer wlan 5 ghz fem ilna 2.4 ghz fem ilna diplexer 5 ghz fem ilna axi backplane jtag ram rom uart 802.11abg n mac radio 22 lcnxnphy core 0 core 1 2.4ghz 2.4ghz 5 ghz 5 ghz gpio uart jtag otp wdt xtal osc lpo sw r eg por ldo features bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 11 features the bcm43243 supports the following features: ? ieee 802.11a/b/g/n dual-band radio?virtual simultaneous dual-band operation ? on-chip wlan driver execution capable of supporting ieee 802.11 functionality ? single- and dual-antenna support ? wlan high-speed usb 2.0 host interface standards compliance the bcm43243 supports the following standards: ? ieee 802.11n?handheld device class (section 11) ? ieee 802.11a, ieee 802.11b, and ieee 802.11g ? ieee 802.11d ? ieee 802.11h ? ieee 802.11i the bcm43243 supports the following future drafts/standards: ? ieee 802.11r?fast roaming (between aps) ? ieee 802.11k?resource management ? ieee 802.11w?secure management frames ? ieee 802.11 extensions: ? ieee 802.11e qos enhancements (as per the wmm ? specification is already supported) ? ieee 802.11h 5 ghz extensions ? ieee 802.11i mac enhancements ? ieee 802.11r fast roaming support ? ieee 802.11k radio resource measurement ? security: ? wlan authentication and privacy infrastructure (wapi) ?wep ?wpa ? personal ?wpa2 ? personal ?wmm ? wmm-ps (u-apsd) ?wmm-sa ? aes (hardware accelerator) ? tkip (hw accelerator) ? ckip (sw support) standards compliance bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 12 ? proprietary protocols: ? ccxv2, ccxv3, ccxv4, and ccxv5 ?wfaec power supplies and power management bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 13 section 2: power supplies and power management power supply topology one buck regulator, multiple ldo regulators, and a power management unit (pmu) are integrated into the bcm43243. all regulators are programmable via the pmu. these blocks simplify power supply design for wlan functions in embedded designs. regulator inputs and outputs are brought out to pins on the bcm43243. this allows maximum flexibility for the system designer to choose which of the bcm43243 integrated regulators to use. a 3.3v regulated supply can be used, with all additional voltages being provided by the regulators in the bcm43243. the wl_reg_on signal is used to power-up the regulators and take the respective section out of reset. the cbuck, cldo, and lnldos power up when any of the reset signals are deasserted. all regulators are powered down only when wl_reg_on is deasserted. the cldo and lnldos may be turned off/on based on the dynamic demands of the digital baseband. the bcm43243 allows for an extremely low power-consumption mode by completely shutting down the cbuck, cldo, and lndlo regulators. when in this state, lpldo1 and lpldo2 (which are low-power linear regulators that are supplied by the system vddio supply) provide the bcm43243 with all the voltages it requires, further reducing leakage currents. bcm43243 pmu features the bcm43243 pmu supplies the following voltages: ? 3.0v to 5.25v (vbat) down to 1.35 vout ? 1.35v to 1.2 vout (150 ma and 325 ma maximum) lnldos ? 1.35v to 1.2 vout (300 ma maximum) cldo ? additional internal ldos (not externally accessible) figure 3 on page 14 shows the regulators and a typical power topology. in this example, vdd33 is an external regulated supply at 3.3v 10%. input to the core buck regulator (vbat) can be tied to vdd33. vddio can also be provided by vdd33. power supply topology bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 14 figure 3: typical power topology shaded areas are internal to the bcm43243 ? wl rf synth/rf pll vdd33 (3.3v) section sensitive to power supply noise loads not sensitive to power supply noise wl_reg_on 1.35v ? wl otp (3.3v) ? wl otp (1.1v) otp 3.3v 1.1v core buck regulator max.600 ma ? vddio_rf for rf switches ? wl digital and mem wl on 1.2v lpldo1 ? always on/state ret island ? clpo/ext. lpo buffer, s dio_aos 2.2uh 0805 ? wl bb pll bb pll 1.2v lnldo1 max.325 ma 4.7 uf 0402 synth ? ipa ? xo ? wl rf - bg 0.80-1.2v lpldo2 1uf 0402 4.7uf 0402 ? wl rf - vco,logen ? wl rf - rx, rcal 4.7uf 0402 cldo max.300 ma ? wl rf - lna ? wl rf - tx ? wl rf - afe lnldo2 max.150 ma 2.2uf 0402 vddio (3.3v) vbat ? vddio (uart/gpio/jtag) wlan power management bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 15 wlan power management all areas of the chip design are optimized to minimize power consumption. silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. additionally, the bcm43243 integrated ram is a high vt memory with dynamic clock control. the dominant supply current consumed by the ram is leakage current only. additionally, the bcm43243 includes an advanced wlan power management unit (pmu) sequencer. the pmu sequencer provides significant power savings by putting the bcm43243 into various power management states appropriate to the current environment and activities that are being performed. the bcm43243 wlan power states are described as follows: ? active mode? all wlan blocks in the bcm43243 are powered up and fully functional with active carrier sensing and frame transmission and receiving. all required regulators are enabled and put in the most efficient mode based on the load current. clock speeds are dynamically adjusted by the pmu sequencer. ? power-down mode?the bcm43243 is effectively powered off by shutting down all internal regulators. the chip is brought out of this mode by external logic, reenabling the internal regulators. pmu sequencing the pmu sequencer is responsible for minimizing system power consumption. it enables and disables various system resources based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. resource requests may come from several sources: clock requests from cores, the minimum resources defined in the resourcemin register, and the resources requested by any active resource request timers. the pmu sequencer maps clock requests into a set of resources required to produce the requested clocks. each resource is in one of four states: enabled, disabled, transition_on, and transition_off and has a timer that contains 0 when the resource is enabled or disabled and a non-zero value in the transition states. the timer is loaded with the time_on or time_off value of the resource when the pmu determines that the resource must be enabled or disabled. that timer decrements on each 32.768 khz pmu clock. when it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. if the time_on value is 0, the resource can go immediately from disabled to enabled. similarly, a time_off value of 0 indicates that the resource can go immediately from enabled to disabled. the terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence. power-up/power-down/reset circuits bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 16 during each clock cycle, the pmu sequencer performs the following actions: ? computes the required resource set based on requests and the resource dependency table. ? decrements all timers whose values are non zero. if a timer reaches 0, the pmu clears the resourcepending bit for the resource and inverts the resourcestate bit. ? compares the request with the current resource status and determines which resources must be enabled or disabled. ? initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered-up dependents. ? initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled. power-up/power-down/reset circuits the bcm43243 has a signal, wl_reg_on, that enables or disables the wlan circuits and the internal regulator blocks, allowing the host to control power consumption. for timing diagrams of these signals and the required power-up sequences, see section 14: ?power-up sequence and timing,? on page 73 . the wl_reg_on signal is used by the pmu to power up the wlan section. when this pin is high, the regulators are enabled and the wlan section is out of reset. when this pin is low, the wlan section is in reset. if wl_reg_on is low, the regulators are disabled. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. frequency references bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 17 section 3: frequency references an external crystal is used for generating all radio frequencies and normal operation clocking. as an alternative, an external frequency reference driven by a temperature-compensated crystal oscillator (tcxo) signal may be used. in addition, a low-power oscillator (lpo) is provided for lower power mode timing. crystal interface and clock generation the bcm43243 can use an external crystal to provide a frequency reference. the recommended configuration for the crystal oscillator including all external components is shown in figure 4 . consult the reference schematics for the latest configuration. figure 4: recommended os cillator configuration a fractional-n synthesizer in the bcm43243 generates the radio frequencies, clocks, and data/packet timing, enabling it to operate using a wide selection of frequency references. the default frequency reference is a 37.4 mhz crystal or tcxo. the signal characteristics for the crystal interface are listed in table 1 on page 19 . note: the crystal and tcxo implementations have different power supplies (wrf_xtal_vdd1p2 for crystal, wrf_tcxo_vdd for tcxo). note: the fractional-n synthesizer can support alternative reference frequencies. frequencies other than the default, however, require support to be added in the driver plus additional extensive system testing. contact broadcom for further details. 12?27 pf 12?27 pf wrf_xtal_on wrf_xtal_o p c c x ohms * * resistor or capacitor value determined by crystal drive level. see reference schematics for details. tcxo bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 18 tcxo as an alternative to a crystal, an external precision tcxo can be used as the frequency reference, provided that it meets the phase noise requirements listed in ta b l e 1 . when the clock is provided by an external tcxo, there are two possible connection methods, shown in figure 5 and figure 6 : 1. if the tcxo is dedicated to driving the bcm43243, it should be connected to the wrf_xtal_op pin through an external 1000 pf coupling capacitor, as shown in figure 5 . the internal clock buffer connected to this pin will be turned off when the bcm43243 goes into sleep mode. when the clock buffer turns on and off there will be a small impedance variation. power must be supplied to the wrf_xtal_vdd1p2 pin. 2. for 2.4 ghz operation only, an alternative is to dc-couple the tcxo to the wrf_tcxo_ck pin, as shown in figure 6 . use this method when the same tcxo is shared with other devices and a change in the input impedance is not acceptable because it may cause a frequency shift that cannot be tolerated by the other device sharing the tcxo. this pin is connected to a clock buffer powered from wrf_tcxo_vdd. if the power supply to this buffer is always on (even in sleep mode), the clock buffer is always on, thereby ensuring a constant input impedance in all states of the device. the maximum current drawn from wrf_tcxo_vdd is approximately 500 a. figure 5: recommended circuit to use with an external dedicated tcxo figure 6: recommended circuit to use with an external shared tcxo tcxo nc 1000 pf wrf_xtal_op wrf_xtal_on wrf_tcxo_ck wrf_tcxo_vd d tcxo nc wrf_tcxo_ck wrf_xtal_on wrf_xtal_op to other devices wrf_tcxo_vdd to always present 1.8v to 1.98v supply tcxo bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 19 table 1: crystal oscillator and external clock ? requirements and performance parameter conditions/notes crystal a a. (crystal) use wrf_xtal_op and wrf_xtal_on, internal power to pin wrf_xtal_vdd1p2. external frequency reference b c b. (tcxo) see ?tcxo? on page 18 for alternative connection methods. c. for a clock reference other than 37.4 mhz, 20 log10(f/ 37.4) db should be added to the limits, where f = the reference clock frequency in mhz. min. typ. max. min. typ. max. units frequency ? ? 37.4 ? ? ? ? mhz crystal load capacitance ? ?12????pf esr ? ??60??? ? drive level external crystal specification requirement 200?????w input impedance (wrf_xtal_op) resistive ? ? ? 12k 17k ? ? capacitive ?????6pf input impedance (wrf_tcxo_in) resistive ? ? ? 17k 31k ? ? capacitive ?????2pf wrf_xtal_op input low level dc-coupled digital signal ? ? ? 0 ? 0.2 v wrf_xtal_op input high level dc-coupled digital signal ? ? ? 1.0 ? 1.26 v wrf_xtal_op input voltage (see figure 5 ) ac-coupled analog signal ? ? ? 400 ? 1200 mv p-p wrf_tcxo_in input voltage (see figure 6 ) dc-coupled analog signal ? ? ? 400 ? 2500 mv p-p frequency tolerance initial + over temp. without trimming ?20 ? 20 ?20 ? 20 ppm duty cycle 37.4 mhz clock ? ? ? 40 50 60 % phase noise (ieee 802.11b/g) 37.4 mhz clock at 10 khz offset ? ? ? ? ? ?131 dbc/hz 37.4 mhz clock at 100 khz or higher offset ? ? ? ? ? ?138 dbc/hz phase noise (ieee 802.11a) 37.4 mhz clock at 10 khz offset ? ? ? ? ? ?139 dbc/hz 37.4 mhz clock at 100 khz or higher offset ? ? ? ? ? ?146 dbc/hz phase noise (ieee 802.11n, 2.4 ghz 37.4 mhz clock at 10 khz offset ? ? ? ? ? ?136 dbc/hz 37.4 mhz clock at 100 khz or higher offset ? ? ? ? ? ?143 dbc/hz phase noise (ieee 802.11n, 5 ghz) 37.4 mhz clock at 10 khz offset ? ? ? ? ? ?144 dbc/hz 37.4 mhz clock at 100 khz or higher offset ? ? ? ? ? ?151 dbc/hz wlan global functions bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 20 section 4: wlan global functions wlan cpu and memory subsystem the bcm43243 includes an integrated arm cortex-m3 ? processor with internal ram and rom. the arm cortex-m3 processor is a low-power processor that features low gate count, low interrupt latency, and low-cost debug. it is intended for deeply embedded applications that require fast interrupt response features. the processor implements the arm architecture v7-m with support for thumb ? -2 instruction set. arm cortex-m3 delivers 30% more performance gain over arm7tdmi. at 0.19 w/mhz, the cortex-m3 is the most power-efficient general-purpose microprocessor available, outperforming 8- and 16-bit devices on mips/w. it supports integrated sleep modes. arm cortex-m3 uses multiple technologies to reduce cost through improved memory utilization, reduced pin overhead, and reduced silicon area. arm cortex-m3 supports independent buses for code and data access (icode/dcode and system buses). arm cortex-m3 supports extensive debug features including real time trace of program execution. on-chip memory for the cpu includes 544 kb ram and 640 kb rom. one-time programmable memory various hardware configuration parameters may be stored in an internal 3072-bit one-time programmable (otp) memory, which is read by the system software after device reset. in addition, customer-specific parameters including the system vendor id and the mac address can be stored, depending on the specific board design. the initial state of all bits in an unprogrammed otp device is 0. after any bit is programmed to a 1, it cannot be reprogrammed to 0. the entire otp array can be programmed in a single write cycle using a utility provided with the broadcom wlan manufacturing test tools. alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state can be altered during each programming cycle. prior to otp programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with the reference board design package. gpio interface bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 21 gpio interface the bcm43243 has 13 general-purpose i/o (gpio) that can be used to connect to various external devices. upon power-up and reset, these pins become tristated. subsequently, they can be programmed to be either input or output pins via the gpio control register. an internal (programmable) pull-up/pull-down resistor is included on each gpio. uart interface one uart interface can be enabled by software as an alternate function on pins uart_rx (muxed on gpio_6) and uart_tx (muxed on gpio_7). provided primarily for debugging during development, this uart enables the bcm43243 to operate as rs-232 data termination equipment (dte) for exchanging and managing data with other serial devices. it is compatible with the industry standard 16550 uart, and it provides a fifo size of 64 8 in each direction. jtag interface the bcm43243 supports the ieee 1149.1 jtag boundary scan standard for performing device package and pcb assembly testing during manufacturing. in addition, the jtag interface allows broadcom to assist customers by using proprietary debug and characterization test tools during board bring-up. therefore, it is highly recommended to provide access to the jtag pins by means of test points or a header on all pcb designs. the jtag interface (multiplexed on the gpio pins) is enabled when the jtag_sel pin is asserted high. the jtag to gpio signal mapping is as follows: ?tck gpio_2 ?tms gpio_3 ?tdi gpio_4 ?tdo gpio_5 usb interface bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 22 section 5: usb interface wlan usb 2.0 interface the bcm43243 usb interface can be set to operate as a usb 2.0 port. features include the following: ? a usb 2.0 protocol engine that supports the following: ? a parallel interface engine (pie) between packet buffers and usb transceiver ? up to nine endpoints, including configurable control endpoint 0 ? separate endpoint packet buffers with a 512-byte fifo buffer each ? host-to-device communication for bulk, control, and interrupt transfers ? configuration and status registers figure 7 shows the blocks in the device core. figure 7: wlan usb 2.0 host interface block diagram the usb 2.0 phy handles the usb protocol and the serial signaling interface between the host and device. it is primarily responsible for data transmission and recovery. on the transmit side, data is encoded, along with a clock, using the nrzi scheme with bit stuffing to ensure that the receiver detects a transition in the data stream. a sync field that precedes each packet enables the receiver to synchronize the data and clock recovery circuits. on the receive side, the serial data is deserialized, unstuffed, and checked for errors. the recovered data and clock are then shifted to the clock domain that is compatible with the internal bus logic. 32-bit on-chip communication system dma engines rx fifo tx fifos tx fifos tx fifos tx fifos tx fifos tx fifos endpoint management unit usb 2.0 protocol engine usb 2.0 phy d+ d- wlan usb 2.0 interface bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 23 the endpoint management unit contains the pie control logic and the endpoint logic. the pie interfaces between the packet buffers and the usb transceiver. it handles packet identification (pid), usb packets, and transactions. the endpoint logic contains nine uniquely addressable endpoints. these endpoints are the source or sink of communication flow between the host and the device. endpoint zero is used as a default control port for both the input and output directions. the usb system software uses this default control method to initialize and configure the device information and allows usb status and control access. endpoint zero is always accessible after a device is attached, powered, and reset. endpoints are supported by 512-byte fifo buffers, one for each in endpoint and one shared by all out endpoints. both tx and rx data transfers support a dma burst of 4, which guarantees low latency and maximum throughput performance. the rx fifo can never overflow by design. the maximum usb packet size cannot be more than 512 bytes. wireless lan mac and phy bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 24 section 6: wireless lan mac and phy mac features the bcm43243 wlan media access controller (mac) supports features specified in the ieee 802.11 base standard, and amended by ieee 802.11n. the salient features are listed below: ? transmission and reception of aggregated mpdus (a-mpdu) ? support for power management schemes, including wmm power-save, power-save multipoll (psmp) and multiphase psmp operation ? support for immediate ack and block-ack policies ? interframe space timing support, including rifs ? support for rts/cts and cts-to-self frame sequences for protecting frame exchanges ? back-off counters in hardware for supporting multiple priorities as specified in the wmm specification ? timing synchronization function (tsf), network allocation vector (nav) maintenance, and target beacon transmission time (tbtt) generation in hardware ? hardware offload for aes-ccmp, legacy wpa tkip, legacy wep ciphers, wapi, and support for key management ? programmable independent basic service set (ibss) or infrastructure basic service set functionality ? statistics counters for mib support mac description the bcm43243 wlan mac is designed to support high-throughput operation with low-power consumption. in addition, several power saving modes have been implemented that allow the mac to consume very little power while maintaining network-wide timing synchronization. the architecture diagram of the mac is shown in figure 8 on page 25 . the following sections provide an overview of the important modules in the mac. mac features bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 25 figure 8: wlan mac architecture psm the programmable state machine (psm) is a microcoded engine, which provides most of the low-level control to the hardware, to implement the ieee 802.11 specification. it is a microcontroller that is highly optimized for flow control operations, which are predominant in implementations of communication protocols. the instruction set and fundamental operations are simple and general, which allows algorithms to be optimized until very late in the design process. it also allows for changes to the algorithms to track evolving ieee 802.11 specifications. the psm fetches instructions from the microcode memory. it uses the shared memory to obtain operands for instructions, as a data store, and to exchange data between both the host and the mac data pipeline (via the shm bus). the psm also uses a scratch-pad memory (similar to a register bank) to store frequently accessed and temporary variables. the psm exercises fine-grained control over the hardware engines by programming internal hardware registers (ihr). these ihrs are colocated with the hardware functions they control and are accessed by the psm via the ihr bus. the psm fetches instructions from the microcode memory using an address determined by the program counter, instruction literal, or a program stack. for alu operations the operands are obtained from shared memory, scratch-pad, ihrs, or instruction literals, and the results are written into the shared memory, scratch- pad, or ihrs. there are two basic branch instructions: conditional branches and alu based branches. to better support the many decision points in the ieee 802.11 algorithms, branches can depend on either a readily available signals from the hardware modules (branch condition signals are available to the psm without polling the ihrs), or the results of alu operations. embedded cpu interface host registers, dma engines tx-fifo (32 kb) wep tkip, aes, wapi txe tx a-mpdu rxe pmq psm shared memory (6 kb) psm ucode memory ext- ihr ifs backoff, btcx tsf nav ihr bus shm bus mac-phy interface rx-fifo (10 kb) rx a-mpdu mac features bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 26 wep the wired equivalent privacy (wep) engine encapsulates all the hardware accelerators to perform the encryption and decryption, as well as mic computation and verification. the accelerators implement the following cipher algorithms: legacy wep, wpa tkip, wpa2 aes-ccmp. the psm determines, based on the frame type and association information, the appropriate cipher algorithm to be used. it supplies the keys to the hardware engines from an on-chip key table. the wep interfaces with the txe to encrypt and compute the mic on transmit frames, and the rxe to decrypt and verify the mic on receive frames. txe the transmit engine (txe) constitutes the transmit data path of the mac. it coordinates the dma engines to store the transmit frames in the txfifo. it interfaces with wep module to encrypt frames and transfers the frames across the mac-phy interface at the appropriate time determined by the channel access mechanisms. the data received from the dma engines are stored in transmit fifos. the mac supports multiple logical queues to support traffic streams that have different qos priority requirements. the psm uses the channel access information from the ifs module to schedule a queue from which the next frame is transmitted. once the frame is scheduled, the txe hardware transmits the frame based on a precise timing trigger received from the ifs module. the txe module also contains the hardware that allows the rapid assembly of mpdus into an a-mpdu for transmission. the hardware module aggregates the encrypted mpdus by adding appropriate headers and pad delimiters as needed. rxe the receive engine (rxe) constitutes the receive data path of the mac. it interfaces with the dma engine to drain the received frames from the rxfifo. it transfers bytes across the mac-phy interface and interfaces with the wep module to decrypt frames. the decrypted data is stored in the rxfifo. the rxe module contains programmable filters that are programmed by the psm to accept or filter frames based on several criteria such as receiver address, bssid, and certain frame types. the rxe module also contains the hardware required to detect a-mpdus, parse the headers of the containers, and disaggregate them into component mpdus. mac features bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 27 ifs the ifs module contains the timers required to determine interframe space timing including rifs timing. it also contains multiple backoff engines required to support prioritized access to the medium as specified by wmm. the interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the phy. these timers provide precise timing to the txe to begin frame transmission. the txe uses this information to send response frames or perform transmit frame-bursting (rifs or sifs separated, as within a txop). the backoff engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or pause the backoff counters. when the backoff counters reach 0, the txe gets notified, so that it may commence frame transmission. in the event of multiple backoff counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies provided by the psm. the ifs module also incorporates hardware that allows the mac to enter a low-power state when operating under the ieee power save mode. in this mode, the mac is in a suspended state with its clock turned off. a sleep timer, whose count value is initialized by the psm, runs on a slow clock and determines the duration over which the mac remains in this suspended state. once the timer expires the mac is restored to its functional state. the psm updates the tsf timer based on the sleep duration ensuring that the tsf is synchronized to the network. tsf the timing synchronization function (tsf) module maintains the tsf timer of the mac. it also maintains the target beacon transmission time (tbtt). the tsf timer hardware, under the control of the psm, is capable of adopting timestamps received from beacon and probe response frames in order to maintain synchronization with the network. the tsf module also generates trigger signals for events that are specified as offsets from the tsf timer, such as uplink and downlink transmission times used in psmp. nav the network allocation vector (nav) timer module is responsible for maintaining the nav information conveyed through the duration field of mac frames. this ensures that the mac complies with the protection mechanisms specified in the standard. the hardware, under the control of the psm, maintains the nav timer and updates the timer appropriately based on received frames. this timing information is provided to the ifs module, which uses it as a virtual carrier- sense indication. mac-phy interface the mac-phy interface consists of a data path interface to exchange rx/tx data from/to the phy. in addition, there is a programming interface, which can be controlled either by the host or by the psm to configure and control the phy. wlan phy description bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 28 wlan phy description the bcm43243 supports ieee 802.11a/b/g/n dual-stream to provide maximum data rates up to 300 mbps. the phy has been designed to work with interference, radio nonlinearity, and impairments. it incorporates efficient implementations of the filters, fft and viterbi decoder algorithms. efficient algorithms have been designed to achieve maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition and tracking, channel estimation and tracking. the phy receiver also contains a robust ieee 802.11b demodulator. the phy carrier sense has been tuned to provide high throughput for ieee 802.11g/11b hybrid networks. phy features ? supports ieee 802.11a, 11b, 11g, and 11n dual-stream phy standards ? ieee 802.11n dual-stream operation in 20 mhz and 40 mhz channels ? supports optional short gi and green field modes in tx and rx ? supports optional space-time block code (stbc) receive of two space-time streams ? supports ieee 802.11h/k for worldwide operation ? advanced algorithms for low power, enhanced sensitivity, range, and reliability ? supports power saving schemes such as single-core listen (ocl), single-core demodulation of siso/ stbc packets based on rssi, and dynamic ml turn-off based on rssi ? automatic gain control scheme for blocking and non blocking application scenario for cellular applications ? closed-loop transmit power control ? digital rf chip calibration algorithms to handle cmos rf chip non-idealities ? on-the-fly channel frequency and transmit power selection ? supports per packet rx antenna diversity for ieee 802.11b phy rates. ? designed to meet fcc and other worldwide regulatory requirements ? tx ldpc for improved range and power efficiency ? hardware support for faster switch times between channels/bands wlan phy description bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 29 figure 9: wlan phy block diagram the phy is capable of fully calibrating the rf front end to extract the highest performance. on power-up, the phy performs a full suite of calibration to correct for iq mismatch and local oscillator leakage. the phy also performs periodic calibration to compensate for any temperature related drift thus maintaining high-performance over time. a closed loop transmit control algorithm maintains the output power to required level with capability control tx power on a per packet basis. one of the key feature of the phy is two space-time stream receive capability. the stbc scheme can obtain diversity gains by using multiple transmit antennas in ap (access point) in a fading channel environment, without increasing the complexity at the sta. details of the stbc receive are shown in the block diagram in figure 10 on page 30 . filters and radio comp frequency and timing synch carrier sense, agc, and rx fsm radio control block common logic block filters and radio comp afe and radio mac interface buffers ofdm demodulate viterbi decoder tx fsm pa comp modulation and coding frame and scramble fft/ifft cck/dsss demodulate descramble and deframe coex modulate/ spread wlan phy description bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 30 figure 10: stbc receive block diagram in stbc mode, symbols are processed in pairs. equalized output symbols are linearly combined and decoded. channel estimate is refined on every pair of symbols using the received symbols and reconstructed symbols. equalizer demod combine demapper viterbi channel h symbol memory weighted averaging estimate channel transmitter fft of 2 symbols descramble and deframe h old h upd h new wlan radio subsystem bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 31 section 7: wlan radio subsystem the bcm43243 includes an integrated dual-band wlan rf transceiver that has been optimized for use in 2.4 ghz and 5 ghz wireless lan systems (but not both simultaneously). it has been designed to provide low- power, low-cost, and robust communications for applications operating in the globally available 2.4 ghz unlicensed ism or 5 ghz u-nii bands. the transmit and receive sections include all on-chip filtering, mixing, and gain control functions. up to 11 rf control signals are available to drive the external rf switches and support external power amplifiers and low noise amplifiers for each band. see the reference board schematics for further details. receiver path the bcm43243 has a wide dynamic range, direct conversion receiver. it employs high order on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz ism band or the entire 5 ghz u-nii band. control signals are available that can support the use of optional external low noise amplifiers (lna), which can increase the receive sensitivity by several db. transmit path baseband data is modulated and upconverted to the 2.4 ghz ism or 5 ghz u-nii bands, respectively. linear on-chip power amplifiers are included for both 2.4 ghz and 5 ghz. closed loop power control is also provided, as are spare rf control signals that can be used to support external rf switches for either or both bands. calibration the bcm43243 features dynamic and automatic on-chip calibration to continually compensate for temperature and process variation across components. this enables the bcm43243 to be used in high-volume applications, because calibration routines are not required during manufacturing testing. these calibration routines are performed periodically in the course of normal radio operation. examples of some of the automatic calibration algorithms are baseband filter calibration for optimum transmit and receive performance and loft calibration for carrier leakage reduction. in addition, i/q calibration, r calibration, and vco calibration are performed on- chip. calibration bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 32 figure 11: radio functional block diagram wl logen wl pll wlan bb clb lpo/ext lpo/rcal wl adc wl 2.4ghz pa driver wl tx g-mixer wl dac wl 5 ghz pa driver wl tx a-mixer wl txlpf wl rxlpf wl rx a-mixer wl rx g-mixer wl a-lna11 wl a-lna12 slna wl g-lna12 shared xo wl txlpf wl dac wl adc wl rxlpf wl atx0 wl grx0 wl gtx0 wl arx0 mux wlan bb wl adc wl 2.4 ghz pa driver wl tx g-mixer wl dac wl 5 ghz pa driver wl tx a-mixer wl txlpf wl rxlpf wl rx a-mixer wl a-lna11 wl a-lna12 slna wl g-lna12 wl txlpf wl dac wl adc wl rxlpf mux wl atx1 wl grx1 wl gtx1 wl arx1 pa pa pa pa broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 33 pinouts and signal descriptions broadcom confidential bcm43243 preliminary data sheet section 8: pinouts and signal descriptions ball map the bcm43243 ball map (top view) is defined in figure 12 through figure 15 on page 36 . figure 12: fcfbga ball map, top view, 1 of 4?a1 through m12 12345678910 11 12 a vss nc nc nc nc nc rf_sw_ctrl_6 b vss vss nc nc nc nc vss nc nc rf_sw_ctrl_7 rf_sw_ctrl_5 c nc nc d nc e nc nc nc vss vss nc nc vss gmode_ext_lna _pu_core0 f nc nc g nc nc rsvd h vss nc j rsvd rsvd gnd otp_vdd33 k rsvd gnd rsvd gnd rsvd vddio_rf l rsvd gnd rsvd vdd m nc gnd gnd gnd gnd vss broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 34 ball map broadcom confidential bcm43243 preliminary data sheet figure 13: fcfbga ball map, top view, 2 of 4?a13 through m23 13 14 15 16 17 18 19 20 21 22 23 rf_sw_ctrl_3 gpio_7 gpio_8 gpio_6 gpio_3 gpio_0 a rf_sw_ctrl_1 rf_sw_ctrl_4 rf_sw_ctrl_2 rf_sw_ctrl_0 gpio_2 jtag_sel gpio_12 gpio_9 gpio_4 gpio_5 gpio_1 b sr_vlx sr_vlx c sr_pvss sr_pvss d amode_ext_lna _pu_core0 ext_xtal_pu sr_pvss sr_pvss e pmu_avss sr_vddbatp5v sr_vddbatp5v f sr_vddbata5v sr_vddbata5v g vout_cldo vout_cldo h gpio_11 wlreg_on vout_lnldo2 vout_lnldo1 vout_lnldo1 j gpio_10 vss vddio vss ldo_vdd1p5 ldo_vdd1p5 k vdd vdd rsvd gnd vss vss l vdd vss monpll avdd33 m broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 35 ball map broadcom confidential bcm43243 preliminary data sheet figure 14: fcfbga ball map, top view, 3 of 4?n1 through ac12 n rsvd gnd gnd vdd p nc gnd gnd gnd vss vdd r wrf_rfin_2g _core0 rgnd rgnd rgnd rgnd rgnd rgnd vss vss t rgnd rgnd rgnd rgnd rgnd rgnd rgnd u wrf_paout_2g _core0 rgnd wrf_rx2g _vdd1p2_core0 rgnd rgnd v rgnd rgnd rgnd rgnd rgnd rgnd w wrf_padrv2g _vdd3p3_core0 rgnd rgnd rgnd rgnd wrf_gpio_out rgnd wrf_afe_vdd1p2 _core0 rgnd wrf_rx2g_vdd1p2 _core1 y rgnd rgnd aa wrf_pa_vdd3p3 _core0 rgnd ab wrf_padrv5g _vdd3p3_core0 rgnd rgnd rgnd rgnd wrf_tx_vdd1p2 _core0 rgnd wrf_rx5g _vdd1p2_core0 rgnd wrf_tx_vdd1p2 _core1 rgnd rgnd ac rgnd wrf_paout _5g_core0 rgnd wrf_rfin _5g_core0 rgnd rgnd wrf_vco _vdd1p2 wrf_synth _vdd1p2 rgnd wrf_rfin _2g_core1 rgnd 12345678910 11 12 broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 36 ball map broadcom confidential bcm43243 preliminary data sheet figure 15: fcfbga ball map, top view, 4 of 4?n13 through ac23 vdd avdd_bbpll rref dp n vdd vdd vss vss vddio_rf vss dm p vss vss vss amode_ext_lna _pu_core1 moncdr dvss r rgnd rgnd rgnd wrf_xtal _cab_gnd1p2 vss vss t rgnd rgnd wrf_xtal _cab_gnd1p2 gmode_ext_lna _pu_core1 rf_sw_ctrl_8 u rgnd rgnd rgnd wrf_xtal _cab_gnd1p2 vss vss v rgnd wrf_afe_vdd1p2 _core1 rgnd rgnd wrf_rx5g _vdd1p2_core1 rgnd wrf_xtal _cab_gnd1p2 wrf_tcxo _vdd1p8 wrf_xtal _cab_xon w wrf_tcxo _ckin2v y wrf_xtal _cab_gnd1p2 wrf_xtal _cab_xop aa rgnd rgnd rgnd rgnd rgnd rgnd rgnd rgnd wrf_xtal _cab_gnd1p2 wrf_xtal _cab_gnd1p2 wrf_xtal _cab_gnd1p2 ab wrf_paout _2g_core1 wrf_padrv2g _vdd3p3_core1 wrf_pa _vdd3p3_core1 wrf_padrv5g _vdd3p3_core1 wrf_paout _5g_core1 rgnd wrf_rfin _5g_core1 rgnd wrf_xtal _cab_gnd1p2 wrf_xtal _cab_vdd1p2 wrf_xtal _cab_gnd1p2 ac 13 14 15 16 17 18 19 20 21 22 23 pin list?ordered by pin number bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 37 pin list?ordered by pin number ta b l e 2 lists the pins numerically by pin number. table 2: pin list by pin number pin name a1 vss a2 nc a4 nc a6 nc a7 nc a9 nc a11 rf_sw_ctrl_6 a13 rf_sw_ctrl_3 a15 gpio_7 a17 gpio_8 a19 gpio_6 a21 gpio_3 a23 gpio_0 b1 vss b2 vss b3 nc b4 nc b5 nc b6 nc b7 vss b8 nc b9 nc b11 rf_sw_ctrl_7 b12 rf_sw_ctrl_5 b13 rf_sw_ctrl_1 b14 rf_sw_ctrl_4 b15 rf_sw_ctrl_2 b16 rf_sw_ctrl_0 b17 gpio_2 b18 jtag_sel b19 gpio_12 b20 gpio_9 b21 gpio_4 b22 gpio_5 b23 gpio_1 c1 nc c2 nc c22 sr_vlx c23 sr_vlx d2 nc_d2 d22 sr_pvss d23 sr_pvss e1 nc e2 nc e5 nc e7 vss e8 vss e9 nc e10 nc e11 vss e12 gmode_ext_lna_pu_core0 e13 amode_ext_lna_pu_core0 e15 ext_xtal_pu e22 sr_pvss e23 sr_pvss f2 nc f5 nc f19 pmu_avss f22 sr_vddbatp5v f23 sr_vddbatp5v g1 nc g2 nc g5 rsvd g22 sr_vddbata5v g23 sr_vddbata5v h2 vss h5 rsvd h22 vout_cldo h23 vout_cldo j1 rsvd pin name pin list?ordered by pin number bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 38 j2 rsvd j8 gnd j10 otp_vdd33 j14 gpio_11 j16 wl_reg_on j19 vout_lnldo2 j22 vout_lnldo1 j23 vout_lnldo1 k1 rsvd k2 gnd k5 rsvd k8 gnd k10 rsvd k11 vddio_rf k13 gpio_10 k14 vss k16 vddio k19 vss k22 ldo_vdd1p5 k23 ldo_vdd1p5 l2 rsvd l5 gnd l10 rsvd l11 vdd l13 vdd l14 vdd l16 rsvd l19 gnd l22 vss l23 vss m1 nc m2 gnd m5 gnd m8 gnd m9 gnd m10 vss m14 vdd m16 vss m19 monpll m22 avdd33 pin name n2 rsvd n5 gnd n9 gnd n12 vdd n14 vdd n19 avdd_bbpll n22 rref n23 dp p1 nc p2 gnd p5 gnd p8 gnd p10 vss p12 vdd p13 vdd p14 vdd p15 vss p16 vss p19 vddio_rf p22 vss p23 dm r1 wrf_rfin_2g_core0 r2 rgnd r5 rgnd r7 rgnd r8 rgnd r9 rgnd r10 rgnd r11 vss r12 vss r13 vss r14 vss r15 vss r19 amode_ext_lna_pu_core1 r22 moncdr r23 gnd t1 rgnd t2 rgnd t5 rgnd t7 rgnd pin name pin list?ordered by pin number bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 39 t8 rgnd t10 rgnd t11 rgnd t13 rgnd t14 rgnd t16 rgnd t17 wrf_xtal_cab_gnd1p2 t19 vss t22 vss u1 wrf_paout_2g_core0 u2 rgnd u5 wrf_rx2g_vdd1p2_core0 u8 rgnd u11 rgnd u13 rgnd u16 rgnd u19 wrf_xtal_cab_gnd1p2 u22 gmode_ext_lna_pu_core1 u23 rf_sw_ctrl_8 v1 rgnd v2 rgnd v5 rgnd v8 rgnd v9 rgnd v11 rgnd v13 rgnd v15 rgnd v16 rgnd v19 wrf_xtal_cab_gnd1p2 v22 vss v23 vss w1 wrf_padrv2g_vdd3p3_core0 w2 rgnd w5 rgnd w6 rgnd w7 rgnd w8 wrf_gpio_out w9 rgnd w10 wrf_afe_vdd1p2_core0 w11 rgnd pin name w12 wrf_rx2g_vdd1p2_core1 w13 rgnd w14 wrf_afe_vdd1p2_core1 w15 rgnd w16 rgnd w17 wrf_rx5g_vdd1p2_core1 w18 rgnd w19 wrf_xtal_cab_gnd1p2 w22 wrf_tcxo_vdd1p8 w23 wrf_xtal_cab_xon y1 rgnd y2 rgnd y22 wrf_tcxo_ckin2v aa1 wrf_pa_vdd3p3_core0 aa2 rgnd aa22 wrf_xtal_cab_gnd1p2 aa23 wrf_xtal_cab_xop ab1 wrf_padrv5g_vdd3p3_core0 ab2 rgnd ab3 rgnd ab4 rgnd ab5 rgnd ab6 wrf_tx_vdd1p2_core0 ab7 rgnd ab8 wrf_rx5g_vdd1p2_core0 ab9 rgnd ab10 wrf_tx_vdd1p2_core1 ab11 rgnd ab12 rgnd ab13 rgnd ab14 rgnd ab15 rgnd ab16 rgnd ab17 rgnd ab18 rgnd ab19 rgnd ab20 rgnd ab21 wrf_xtal_cab_gnd1p2 ab22 wrf_xtal_cab_gnd1p2 ab23 wrf_xtal_cab_gnd1p2 pin name pin list?ordered by pin number bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 40 ac1 rgnd ac2 wrf_paout_5g_core0 ac3 rgnd ac4 wrf_rfin_5g_core0 ac5 rgnd ac6 rgnd ac7 wrf_vco_vdd1p2 ac9 wrf_synth_vdd1p2 ac10 rgnd ac11 wrf_rfin_2g_core1 ac12 rgnd ac13 wrf_paout_2g_core1 ac14 wrf_padrv2g_vdd3p3_core1 ac15 wrf_pa_vdd3p3_core1 ac16 wrf_padrv5g_vdd3p3_core1 ac17 wrf_paout_5g_core1 ac18 rgnd ac19 wrf_rfin_5g_core1 ac20 rgnd ac21 wrf_xtal_cab_gnd1p2 ac22 wrf_xtal_cab_vdd1p2 ac23 wrf_xtal_cab_gnd1p2 pin name pin list?listed alphabetically by pin name bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 41 pin list?listed alphabetically by pin name ta b l e 3 lists the pins alphabetically by pin name. table 3: alphabetical pin list by pin name name pin amode_ext_lna_pu_core0 e13 amode_ext_lna_pu_core1 r19 avdd33 m22 avdd_bbpll n19 dm p23 dp n23 ext_xtal_pu e15 gmode_ext_lna_pu_core0 e12 gmode_ext_lna_pu_core1 u22 gnd j8 gnd k2 gnd k8 gnd l5 gnd l19 gnd m2 gnd m5 gnd m8 gnd m9 gnd n5 gnd n9 gnd p2 gnd p5 gnd p8 gnd r23 gpio_0 a23 gpio_1 b23 gpio_2 b17 gpio_3 a21 gpio_4 b21 gpio_5 b22 gpio_6 a19 gpio_7 a15 gpio_8 a17 gpio_9 b20 gpio_10 k13 gpio_11 j14 gpio_12 b19 jtag_sel b18 ldo_vdd1p5 k22 ldo_vdd1p5 k23 moncdr r22 monpll m19 nc a2 nc a4 nc a6 nc a7 nc a9 nc b3 nc b4 nc b5 nc b6 nc b8 nc b9 nc c1 nc c2 nc d2 nc e1 nc e2 nc e5 nc e9 nc e10 nc f2 nc f5 nc g1 nc g2 nc m1 nc p1 otp_vdd33 j10 pmu_avss f19 rf_sw_ctrl_0 b16 name pin pin list?listed alphabetically by pin name bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 42 rf_sw_ctrl_1 b13 rf_sw_ctrl_2 b15 rf_sw_ctrl_3 a13 rf_sw_ctrl_4 b14 rf_sw_ctrl_5 b12 rf_sw_ctrl_6 a11 rf_sw_ctrl_7 b11 rf_sw_ctrl_8 u23 rgnd r2 rgnd r5 rgnd r7 rgnd r8 rgnd r9 rgnd r10 rgnd t1 rgnd t2 rgnd t5 rgnd t7 rgnd t8 rgnd t10 rgnd t11 rgnd t13 rgnd t14 rgnd t16 rgnd u2 rgnd u8 rgnd u11 rgnd u13 rgnd u16 rgnd v1 rgnd v2 rgnd v5 rgnd v8 rgnd v9 rgnd v11 rgnd v13 rgnd v15 rgnd v16 rgnd w2 rgnd w5 name pin rgnd w6 rgnd w7 rgnd w9 rgnd w11 rgnd w13 rgnd w15 rgnd w16 rgnd w18 rgnd y1 rgnd y2 rgnd aa2 rgnd ab2 rgnd ab3 rgnd ab4 rgnd ab5 rgnd ab7 rgnd ab9 rgnd ab11 rgnd ab12 rgnd ab13 rgnd ab14 rgnd ab15 rgnd ab16 rgnd ab17 rgnd ab18 rgnd ab19 rgnd ab20 rgnd ac1 rgnd ac3 rgnd ac5 rgnd ac6 rgnd ac10 rgnd ac12 rgnd ac18 rgnd ac20 rref n22 rsvd g5 rsvd h5 rsvd j1 rsvd j2 name pin pin list?listed alphabetically by pin name bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 43 rsvd k1 rsvd k5 rsvd k10 rsvd l2 rsvd l10 rsvd l16 rsvd n2 sr_pvss d22 sr_pvss d23 sr_pvss e22 sr_pvss e23 sr_vddbata5v g22 sr_vddbata5v g23 sr_vddbatp5v f22 sr_vddbatp5v f23 sr_vlx c22 sr_vlx c23 vdd l11 vdd l13 vdd l14 vdd m14 vdd n12 vdd n14 vdd p12 vdd p13 vdd p14 vddio k16 vddio_rf k11 vddio_rf p19 vout_cldo h22 vout_cldo h23 vout_lnldo1 j22 vout_lnldo1 j23 vout_lnldo2 j19 vss a1 vss b1 vss b2 vss b7 vss e7 vss e8 name pin vss e11 vss h2 vss k14 vss k19 vss l22 vss l23 vss m10 vss m16 vss p10 vss p15 vss p16 vss p22 vss r11 vss r12 vss r13 vss r14 vss r15 vss t19 vss t22 vss v22 vss v23 wl_reg_on j16 wrf_afe_vdd1p2_core0 w10 wrf_afe_vdd1p2_core1 w14 wrf_gpio_out w8 wrf_padrv2g_vdd3p3_core0 w1 wrf_padrv2g_vdd3p3_core1 ac14 wrf_padrv5g_vdd3p3_core0 ab1 wrf_padrv5g_vdd3p3_core1 ac16 wrf_paout_2g_core0 u1 wrf_paout_2g_core1 ac13 wrf_paout_5g_core0 ac2 wrf_paout_5g_core1 ac17 wrf_pa_vdd3p3_core0 aa1 wrf_pa_vdd3p3_core1 ac15 wrf_rfin_2g_core0 r1 wrf_rfin_2g_core1 ac11 wrf_rfin_5g_core0 ac4 wrf_rfin_5g_core1 ac19 wrf_rx2g_vdd1p2_core0 u5 name pin pin list?listed alphabetically by pin name bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 44 wrf_rx2g_vdd1p2_core1 w12 wrf_rx5g_vdd1p2_core0 ab8 wrf_rx5g_vdd1p2_core1 w17 wrf_synth_vdd1p2 ac9 wrf_tcxo_ckin2v y22 wrf_tcxo_vdd1p8 w22 wrf_tx_vdd1p2_core0 ab6 wrf_tx_vdd1p2_core1 ab10 wrf_vco_vdd1p2 ac7 wrf_xtal_cab_gnd1p2 t17 wrf_xtal_cab_gnd1p2 u19 wrf_xtal_cab_gnd1p2 v19 wrf_xtal_cab_gnd1p2 w19 wrf_xtal_cab_gnd1p2 aa22 wrf_xtal_cab_gnd1p2 ab21 wrf_xtal_cab_gnd1p2 ab22 wrf_xtal_cab_gnd1p2 ab23 wrf_xtal_cab_gnd1p2 ac21 wrf_xtal_cab_gnd1p2 ac23 wrf_xtal_cab_vdd1p2 ac22 wrf_xtal_cab_xon w23 wrf_xtal_cab_xop aa23 name pin signal descriptions bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 45 signal descriptions the signal name, type, and description of each pin in the bcm43243 is listed in ta b l e 4 . the type indicates pin direction (i/o = bidirectional, i = input, o = output) and the internal pull-up/pull-down characteristics (pu = weak internal pull-up resistor and pd = weak internal pull-down resistor), if any. table 4: fcfbga signal descriptions signal name fcfbga ball # type description wlan radio pins avdd_bbpll n19 i baseband pll supply wrf_xtal_cab_xon w23 o xtal output wrf_xtal_cab_xop aa23 i xtal input wrf_rfin_2g_core1 ac11 i 2.4g rf input core 1 wrf_rfin_5g_core1 ac19 i 5g rf input core 1 wrf_gpio_out w8 o wlan radio gpio wrf_tcxo_ckin2v y22 i tcxo buffered input. when not using a tcxo this pin should be connected to ground. wrf_synth_vdd1p2 ac9 i clock and miscellaneous supplies wrf_tcxo_vdd1p8 w22 wrf_vco_vdd1p2 ac7 wrf_xtal_cab_vdd1p2 ac22 wrf_xtal_cab_gnd1p2 t17, u19, v19, w19, aa22, ab21, ab22, ab23, ac21, ac23 i clock and miscellaneous grounds wrf_afe_vdd1p2_core1 w14 i wlan core 1 radio supplies wrf_padrv2g_vdd3p3_core1 ac14 wrf_padrv5g_vdd3p3_core1 ac16 wrf_tx_vdd1p2_core1 ab10 wrf_rx2g_vdd1p2_core1 w12 wrf_rx5g_vdd1p2_core1 w17 wrf_rfin_2g_core0 r1 i 2.4g rf input core 0 wrf_rfin_5g_core0 ac4 i 5g rf input core 0 wrf_paout_2g_core0 u1 o 2.4 ghz rf output for core 0 wrf_paout_2g_core1 ac13 o 2.4 ghz rf output for core 1 wrf_paout_5g_core0 ac2 o 5 ghz rf output for core 0 wrf_paout_5g_core1 ac17 o 5 ghz rf output for core 1 signal descriptions bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 46 wrf_afe_vdd1p2_core0 w10 i wlan core 0 radio supplies wrf_padrv2g_vdd3p3_core0 w1 wrf_padrv5g_vdd3p3_core0 ab1 wrf_tx_vdd1p2_core0 ab6 wrf_rx2g_vdd1p2_core0 u5 wrf_rx5g_vdd1p2_core0 ab8 wrf_pa_vdd3p3_core1 ac15 i wlan pa supplies (core 1) wrf_pa_vdd3p3_core0 aa1 i wlan pa supplies (core 0) wlan digital pins rf_sw_ctrl_0 b16 o wlan rf switch control outputs rf_sw_ctrl_1 b13 rf_sw_ctrl_2 b15 rf_sw_ctrl_3 a13 rf_sw_ctrl_4 b14 rf_sw_ctrl_5 b12 rf_sw_ctrl_6 a11 rf_sw_ctrl_7 b11 rf_sw_ctrl_8 u23 gmode_ext_lna_pu_core0 e12 o 2.4g external lna control core 0 amode_ext_lna_pu_core0 e13 o 5g external lna control core 0 gmode_ext_lna_pu_core1 u22 o 2.4g external lna control core 1 amode_ext_lna_pu_core1 r19 o 5g external lna control core 1 gpio_11 j14 i/o wlan gpio gpio_10 k13 i/o wlan gpio gpio_9 b20 i/o wlan gpio gpio_8 a17 i/o wlan gpio gpio_7 a15 i/o wlan gpio gpio_12 b19 i/o this pin can be programmed to be a gpio or the jtag trst_l signal. gpio_6 a19 i/o wlan gpio gpio_5 b22 i/o this pin can be programmed to be a gpio or the jtag tdo signal. gpio_4 b21 i/o this pin can be programmed to be a gpio or the jtag tdi signal. gpio_3 a21 i/o this pin can be programmed to be a gpio or the jtag tms signal. gpio_2 b17 i/o this pin can be programmed to be a gpio or the jtag tck signal. gpio_1 b23 i/o this pin can be programmed to be a gpio or ap_ready. table 4: fcfbga signal descriptions (cont.) signal name fcfbga ball # type description signal descriptions bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 47 gpio_0 a23 i/o this pin can be programmed to be a gpio or a wlan_host_wake output indicating that host wake-up should be performed. jtag_sel b18 i jtag select. the jtag interface (multiplexed on the gpio pins) is enabled when this pin is asserted high. ext_xtal_pu e15 o external xtal oscillator power-up signal vdd l11, l13, l14, m14, n12, n14, p12?p14 i digital always-on core supply otp_vdd33 j10 i 3.3v otp power supply vddio k16 i 3.3v i/o supply vddio_rf k11, p19 i 3.3v rf control i/o supply vss a1, b1, b2, b7, e7, e8, e11, h2, k14, k19, l22, l23, m10, m16, p10, p15, p16, p22, r11?r15, t19, t22, v22, v23 i core ground rgnd r2, r5, r7?r10, t1, t2, t5, t7, t8, t10, t11, t13, t14, t16, u2, u8, u11, u13, u16, v1, v2, v5, v8, v9, v11, v13, v15, v16, w2, w5?7, w9, w11, w13, w15, w16, w18, y1, y2, aa2, ab2?ab5, ab7, ab9, ab11? ab20, ac1, ac3, ac5, ac6, ac10, ac12, ac18, ac20 i wlan radio ground wlan usb pins dp n23 ? data+ dm p23 ? data? moncdr r22 ? usb 2.0 debug monpll m19 ? usb 2.0 debug rref n22 ? usb 2.0 reference resistor avdd33 m22 ? usb 2.0 3.3v supply pmu pins table 4: fcfbga signal descriptions (cont.) signal name fcfbga ball # type description signal descriptions bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 48 sr_pvss d22, d23, e22, e23 i switcher ground sr_vddbata5v g22, g23 i battery voltage input for band-gap and ldo3p3 sr_vddbatp5v f22, f23 i battery voltage input for the cbuck switcher sr_vlx c22, c23 o switcher output (1.35v default) ldo_vdd1p5 k22, k23 i ldo input for cldo, lnldo1, and lnldo2. also voltage feedback input for cbuck. (1.35v default) wl_reg_on j16 i used by pmu to power up or power down the internal bcm43243 regulators used by the wlan section. also, when deasserted, this pin holds the wlan section in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. pmu_avss f19 i pmu ground vout_lnldo1 j22, j23 o 1.2v lnldo1 output vout_lnldo2 j19 o 1.2v lnldo2 output vout_cldo h22, h23 o 1.2v digital core ldo output ground pins gnd j8, k2, k8, l5, l19, m2, m5, m8, m9, n5, n9, p2, p5, p8, r23 ? connect to ground. no-connect pins nc a2, a4, a6, a7, a9, b3, b4, b5, b6, b8, b9, c1, c2, d2, e1, e2, e5, e9, e10, f2, f5, g1, g2, m1, p1 ? no-connect reserved pins rsvd l16 ? reserved. connect a 0 ? pull-down resistor to this pin. rsvd h5, j8, k2, k8, l5, l19, m2, m5, m8, m9, n5, n9, p2, p5, p8, r23 ? reserved. connect to ground. rsvd j1, j2, k1, k5, l2 ? reserved. connects to vout_lnldo2. rsvd k10, l10 reserved. connects to vout_cldo rsvd g5, n2 ? reserved. connect these pins to 3.3v. table 4: fcfbga signal descriptions (cont.) signal name fcfbga ball # type description signal descriptions bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 49 wlan gpio signals and strapping options the pins listed in table 5 are sampled at power-on reset (por) to determine various operating modes. sampling occurs a few milliseconds after an internal por or deassertion of the external por. after the por, each pin assumes the gpio or alternative function specified in the signal descriptions table. each strapping option pin has an internal pull-up (pu) or pull-down (pd) resistor that determines the default mode. to change the mode, connect an external pu resistor to vddio or a pd resistor to gnd, using a 10 k ? resistor or less. note: refer to the reference board schematics for more information. table 5: wlan gpio functions and strapping options pin name(s) fcfbg a pin function default description gpio_6, amode_ext_ lna_pu_core 0 a19 e13 strap_host_ifc_2 strap_host_ifc_1 00 the 2 strap pins strap_host_ifc_[2:1] together select the host interface to enable: 00: normal usb 01: bootloader-less usb gpio_7 a15 otpenabled 1 when this bit is 0, the otp memory is not powered up by default. gpio_8 a17 sflash present 0 sflash present strap gpio_9 b20 arm remap[0] 1 0: boot from sram, arm held in reset. 1: boot from rom by remapping the arm core exception vectors, with the arm held in reset. gpio_10 k13 sflash type 0 type of sflash used: 1 = atmel ? , 0 = st ? gpio_0, gpio_1 a23 b23 resourceinitmode[1:0] 10 00: pmu to power up to ilp clock available (no backplane clock). 01: power up to ilp clock request. 10: alp clock available. 11: ht clock available. this field may not be set to 11 for implementations using an oscillator running at other than 30 mhz because the pll must be reprogrammed before it is enabled. ext_xtal_pu e15 strap_ext_xtal_pu_pol 0 this strap defines the output polarity of the ext_xtal_pu signal. 0 = active high output polarity. 1 = active low output polarity. broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 50 i/o states broadcom confidential bcm43243 preliminary data sheet i/o states the following notations are used in ta b l e 6 : ? i: input signal ? o: output signal ? i/o: input/output signal ?pu = pulled up ? pd = pulled down ? nopull = neither pulled up nor pulled down table 6: i/o states name i/o keeper active mode low power state/sleep (all power present) power-down (wl_reg_on held low) out-of-reset; before sw download (wl_reg_on high) wl_reg_on high and vddios are present power rail wl_reg_on i n input; pd (pull-down can be disabled) input; pd (pull-down can be disabled) input; pd (of 200k) input; pd (of 200k) input; pd (of 200k) ? gpio_0 i/o y input/output; pu, pd, nopull (programmable [default: pd]) input/output; pu, pd, nopull (programmable [default: pd]) high-z, nopull input; pd input; pd wl_vddio gpio_1 i/o y input/output; pu, pd, nopull (programmable [default: pu]) input/output; pu, pd, nopull (programmable [default: pu]) high-z, nopull input; pu input; pu wl_vddio gpio_2 i/o y input/output; pu, pd, nopull (programmable [default: pu]) input/output; pu, pd, nopull (programmable [default: pu]) high-z, nopull input; pu input; pu wl_vddio gpio_3 i/o y input/output; pu, pd, nopull (programmable [default: pu]) input/output; pu, pd, nopull (programmable [default: pu]) high-z, nopull input; pu input; pu wl_vddio gpio_4 i/o y input/output; pu, pd, nopull (programmable [default: nopull]) input/output; pu, pd, nopull (programmable [default: nopull]) high-z, nopull input; nopull input; nopull wl_vddio gpio_5 i/o y input/output; pu, pd, nopull (programmable [default: pu]) input/output; pu, pd, nopull (programmable [default: pu]) high-z, nopull input; pu input; pu wl_vddio gpio_6 i/o y input/output; pu, pd, nopull (programmable [default: pd]) input/output; pu, pd, nopull (programmable [default: pd]) high-z, nopull input; pd input; pd wl_vddio broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 51 i/o states broadcom confidential bcm43243 preliminary data sheet note: 1. keeper column: n=pad has no keeper. y=pad has a keeper. keeper is always active except in power-down state. 2. if there is no keeper, and it is an input and there is nopull, then the pad should be driven to prevent leakage due to floating pad (sdio_clk, for example). 3. in the power-down state (xx_reg_on=0): high-z; nopull => the pad is disabled because power is not supplied. table 6: i/o states (cont.) name i/o keeper active mode low power state/sleep (all power present) power-down (wl_reg_on held low) out-of-reset; before sw download (wl_reg_on high) wl_reg_on high and vddios are present power rail dc characteristics bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 52 section 9: dc characteristics absolute maximum ratings note: values in this data sheet are design goals and are subject to change based on the results of device characterization. caution! the absolute maximum ratings in table 7 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. functional operation is not guaranteed under these conditions. operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. table 7: absolute maximum ratings rating symbol value unit dc supply voltage for i/o vddio ?0.5 to 3.8 v dc supply voltage for rf vddrf ?0.5 to 1.32 v dc supply voltage for core vddc ?0.5 to 1.32 v dc supply voltage for rf i/os and pa driver supply vddio_rf ?0.5 to 3.8 v dc supply voltage for battery-supplied pins sr_vddbata5v (vbat) ?0.5 to 5.25 v dc input supply voltage for cldo and lnldo1 ? ?0.5 to 2.1 v wrf_tcxo_vdd ? ?0.5 to 1.98 v maximum undershoot voltage for i/o v undershoot ?0.5 v maximum junction temperature t j 125 c environmental ratings bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 53 environmental ratings the environmental ratings are shown in table 8 . electrostatic discharge specifications extreme caution must be exercised to prevent electrostatic discharge (esd) damage. proper use of wrist and heel grounding straps to discharge static electricity is required when handling these devices. always store unused material in its antistatic packaging. table 8: environmental ratings characteristic value units conditions/comments ambient temperature (t a ) 0 to +70 c functional operation a a. functionality is guaranteed but specifications require derating at extreme temperatures; see the specification tables for details. storage temperature ?40 to +125 c ? relative humidity less than 60 % storage less than 85 % operation table 9: esd specifications pin type symbol condition esd rating unit esd, handling reference: nqy00083, section 3.4, group d9, table b esd_hand_hbm human body model contact discharge per jedec eid/jesd22-a114 1000 v machine model (mm) esd_hand_mm machine model contact 75 v cdm esd_hand_cdm charged device model contact discharge per jedec eia/jesd22-c101 500 v recommended operating conditions and dc characteristics bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 54 recommended operating conditi ons and dc characteristics caution! functional operation is not guaranteed outside of the limits shown in ta b l e 1 0 and operation outside these limits for extended periods can adversely affect long-term reliability of the device. table 10: recommended operating conditions and dc characteristics parameter symbol value unit minimum typical maximum dc supply voltage vdd33 3.0 3.3 3.6 v dc supply voltage vddio 3.0 3.3 3.6 v dc supply voltage for cbuck vbat 3.0 3.3 5.25 v dc supply voltage for core vdd 1.14 1.2 1.26 v dc supply voltage for rf blocks in chip vddrf 1.14 1.2 1.26 v dc supply voltage for tcxo input buffer wrf_tcxo_vd d 1.62 1.8 1.98 v other digital i/o pins for vddio = 3.3v: input high voltage vih 2.00 ? ?v input low voltage vil ? ?0.80v output high voltage @ 2 ma voh vddio ? 0.4 ? ?v output low voltage @ 2 ma vol ? ?0.40v rf switch control output pins for vddio_rf = 3.3v: output high voltage @ 2 ma voh vddio ? 0.4 ? ?v output low voltage @ 2 ma vol ? ?0.40v input capacitance c in ? ? 5 pf wlan rf specifications bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 55 section 10: wlan rf specifications introduction the bcm43243 includes an integrated dual-band direct conversion radio that supports either the 2.4 ghz band or the 5 ghz band. this section describes the rf characteristics of the 2.4 ghz and 5 ghz portions of the radio. unless otherwise stated, limit values apply for the conditions specified in table 8: ?environmental ratings,? on page 53 and table 10: ?recommended operating conditions and dc characteristics,? on page 54 . typical values apply for the following conditions: ? vdd33 = 3.3v 10% (vbat tied to vdd33) ? ambient temperature +25c figure 16: port locations note: values in this data sheet are design goals and are subject to change based on the results of device characterization. note: all wlan specifications are measured at the chip port, unless otherwise specified. filter bcm43243 rf switch (0.5 db insertion loss) antenna port rf port wlan tx wlan rx chip port 2.4 ghz band general rf specifications bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 56 2.4 ghz band general rf specifications wlan 2.4 ghz receiver perf ormance specifications table 11: 2.4 ghz band general rf specifications item condition minimum typical maximum unit tx/rx switch time including tx ramp down ? ? 5 s rx/tx switch time including tx ramp up ? ? 2 s power-up and power-down ramp time dsss/cck modulations ? ? < 2 s note: the specifications in ta b le 1 2 are measured at the chip port, unless otherwise specified. table 12: wlan 2.4 ghz receiver performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz siso rx sensitivity (8% per for 1024 octet psdu) 1 mbps dsss ? ?99.0 ? dbm 2 mbps dsss ? ?96.0 ? dbm 5.5 mbps dsss ? ?94.2 ? dbm 11 mbps dsss ? ?90.4 ? dbm siso rx sensitivity (10% per for 1024 octet psdu) 6 mbps ofdm ? ?94.0 ? dbm 9 mbps ofdm ? ?93.1 ? dbm 12 mbps ofdm ? ?91.7 ? dbm 18 mbps ofdm ? ?89.6 ? dbm 24 mbps ofdm ? ?85.6 ? dbm 36 mbps ofdm ? ?83 ? dbm 48 mbps ofdm ? ?77.7 ? dbm 54 mbps ofdm ? ?76.5 ? dbm mimo rx sensitivity (10% per for 1024 octet psdu) 6 mbps ofdm ? ?95.0 ? dbm/core 9 mbps ofdm ? ?94.2 ? dbm/core 12 mbps ofdm ? ?93.5 ? dbm/core 18 mbps ofdm ? ?92.6 ? dbm/core 24 mbps ofdm ? ?88.6 ? dbm/core 36 mbps ofdm ? ?86 ? dbm/core 48 mbps ofdm ? ?81.1 ? dbm/core 54 mbps ofdm ? ?80.1 ? dbm/core wlan 2.4 ghz receiver performance specifications bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 57 siso rx sensitivity (10% per for 4096 octet psdu) a. defined for default parameters: gf, 800 ns gi, and non-stbc. 20 mhz channel spacing for all mcs rates mcs 7 ? ?73.9 ? dbm mcs 6 ? ?75.6 ? dbm mcs 5 ? ?77 ? dbm mcs 4 ? ?81.4 ? dbm mcs 3 ? ?84.5 ? dbm mcs 2 ? ?88.3 ? dbm mcs 1 ? ?90.5 ? dbm mcs0 ? ?92.5 ? dbm mimo rx sensitivity (10% per for 4096 octet psdu) a. defined for default parameters: gf, 800 ns gi, and non-stbc. 20 mhz channel spacing for all mcs rates mcs 15 ? ?70.4 ? dbm (total) mcs 8 ? ?90.1 ? dbm (total) mcs 7 ? ?76.9 ? dbm/core mcs 6 ? ?78.6 ? dbm/core mcs 5 ? ?80 ? dbm/core mcs 4 ? ?84.4 ? dbm/core mcs 3 ? ?87.5 ? dbm/core mcs 2 ? ?91.1 ? dbm/core mcs 1 ? ?93.2 ? dbm/core mcs0 ? ?94.0 ? dbm/core blocking level for 1 db rx sensitivity degradation (without external filtering) b 776?794 mhz cdma2000 ?20 ? ? dbm 824?849 mhz c cdmaone ?24.5 ? ? dbm 824?849 mhz gsm850 ?20 ? ? dbm 880?915 mhz e-gsm ?18 ? ? dbm 1710?1785 mhz gsm1800 ?20 ? ? dbm 1850?1910 mhz gsm1800 ?22 ? ? dbm 1850?1910 mhz cdmaone ?32 ? ? dbm 1850?1910 mhz wcdma ?29 ? ? dbm 1920?1980 mhz wcdma ?32 ? ? dbm in-band static cw jammer immunity (fc ? 8 mhz < fcw < + 8 mhz) rx per < 1%, 54 mbps ofdm, 1000 octet psdu for: (rxsense + 23 db < rxlevel < max input level) ?80 ? ? dbm input in-band ip3 maximum lna gain ? ?15.5 ? dbm minimum lna gain ? ?1.5 ? dbm maximum receive level @ 2.4 ghz @ 1, 2 mbps (8% per, 1024 octets) ?3.5 ? ? dbm @ 5.5, 11 mbps (8% per, 1024 octets) ?9.5 ? ? dbm @ 6?54 mbps (10% per, 1024 octets) ?19.5 ? ? dbm @ mcs0?7 rates (10% per, 4095 octets) ?19.5 ? ? dbm table 12: wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit wlan 2.4 ghz receiver performance specifications bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 58 lpf 3 db bandwidth ? 9 ? 10 mhz adjacent channel rejection-dsss (difference between interfering and desired signal at 8% per for 1024 octet psdu with desired signal level as specified in condition/notes) desired and interfering signal 30 mhz apart 1 mbps dsss ?74 dbm 35 ? ? db 2 mbps dsss ?74 dbm 35 ? ? db desired and interfering signal 25 mhz apart 5.5 mbps dsss ?70 dbm 35 ? ? db 11 mbps dsss ?70 dbm 35 ? ? db adjacent channel rejection-ofdm (difference between interfering and desired signal (25 mhz apart) at 10% per for 1024 octet psdu with desired signal level as specified in condition/notes) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db adjacent channel rejection mcs0?7 (difference between interfering and desired signal (25 mhz apart) at 10% per for 4096 octet psdu with desired signal level as specified in condition/notes) mcs7 ?61 dbm ?2 ? ? db mcs6 ?62 dbm ?1 ? ? db mcs5 ?63 dbm 0 ? ? db mcs4 ?67 dbm 4 ? ? db mcs3 ?71 dbm 8 ? ? db mcs2 ?74 dbm 11 ? ? db mcs1 ?76 dbm 13 ? ? db mcs0 ?79 dbm 16 ? ? db maximum receiver gain ? ? ? 105 ? db gain control step ? ? ? 3 ? db rssi accuracy d range ?95 dbm to ?30 dbm ?5 ? 5 db range above ?30 dbm ?8 ? 8 db return loss z o = 50 ? , across the dynamic range 6 10 ? db receiver cascaded noise figure at maximum gain ? 3.5 ? db a. sensitivity degradations for alternate settings in mcs modes. mm: 0.5 db drop, sgi: 2 db drop, and stbc: 0.75 db drop. b. the cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose of this test. it is not intended to indicate any specific usage of each band in any specific country. c. the blocking levels are valid for channels 1 to 11. (for higher channels, the performance may be lower due to third harmonic signals (3 824 mhz) falling within band.) d. the minimum and maximum values shown have a 95% confidence level. table 12: wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit wlan 2.4 ghz transmitter performance specifications bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 59 wlan 2.4 ghz transmitter performance specifications note: the specifications in table 13 are measured at the chip port output, unless otherwise specified. table 13: wlan 2.4 ghz transmitter performance specifications a a. all power targets are measured at the chip output and were measured using revision 6 reference boards. parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz harmonic level (at ?5 dbm with 100% duty cycle) 4.8?5.0 ghz 2nd harmonic ? ? tbd dbm/ 1mhz 7.2?7.5 ghz 3rd harmonic ? ? tbd dbm/ 1mhz ofdm evm ofdm, 64 qam 0 dbm ? ?31 ? db ofdm evm ofdm, 64 qam ?3 dbm ? ?33.9 ? db ofdm evm mcs7 ?6 dbm ? ?35 ? db tx power at chip port for highest power level setting at 25c, vdd33 = 3.3v, spectral mask and evm compliance b b. derate by 1 db for pa_vdd supply (direct supply to pa) of 3v. ieee 802.11b: 1 mbps ? 19.0 ? dbm ieee 802.11g: 6 mbps ? 22.5 ? dbm ieee 802.11g: 54 mbps @ 25 db evm, siso + cdd ? 18.5 ? dbm mcs7: ht20 @ 28 db evm, siso + cdd ? 17.0 ? dbm mcs7: ht40 @ 28 db evm, siso + cdd ? 17.0 ? dbm phase noise 37.4 mhz crystal, integrated from 10 khz to 10 mhz ? 0.5 ? degrees tx power control dynamic range ?10??db carrier suppression ? 15 ? ? dbc gain control step ? ? 0.25 ? db return loss at chip port tx z o = 50 ? 46?db wlan 5 ghz receiver performance specifications bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 60 wlan 5 ghz receiver performance specifications note: the specifications in ta b le 1 4 are measured at the chip port input, unless otherwise specified. table 14: wlan 5 ghz receiver performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 4900 ? 5845 mhz siso rx sensitivity (10% per for 1000 octet psdu) 6 mbps ofdm ? ?92.4 ? dbm 9 mbps ofdm ? ?91.1 ? dbm 12 mbps ofdm ? ?89.7 ? dbm 18 mbps ofdm ? ?87.6 ? dbm 24 mbps ofdm ? ?83.6 ? dbm 36 mbps ofdm ? ?81 ? dbm 48 mbps ofdm ? ?76.2 ? dbm 54 mbps ofdm ? ?75.1 ? dbm mimo rx sensitivity (10% per for 1000 octet psdu) 6 mbps ofdm ? ?93.5 ? dbm/core 9 mbps ofdm ? ?88.3 ? dbm/core 12 mbps ofdm ? ?86.7 ? dbm/core 18 mbps ofdm ? ?84.5 ? dbm/core 24 mbps ofdm ? ?80.8 ? dbm/core 36 mbps ofdm ? ?78 ? dbm/core 48 mbps ofdm ? ?73.4 ? dbm/core 54 mbps ofdm ? ?78.0 ? dbm/core siso rx sensitivity (10% per for 4096 octet psdu) defined for default parameters: gf, 800 ns gi, and non- stbc. 20 mhz channel spacing for all mcs rates mcs 7 ? ?71.9 ? dbm mcs 6 ? ?73.6 ? dbm mcs 5 ? ?75 ? dbm mcs 4 ? ?79.4 ? dbm mcs 3 ? ?82.5 ? dbm mcs 2 ? ?86.3 ? dbm mcs 1 ? ?88.5 ? dbm mcs 0 ? ?90.5 ? dbm wlan 5 ghz receiver performance specifications bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 61 mimo rx sensitivity (10% per for 4096 octet psdu) defined for default parameters: gf, 800 ns gi, and non- stbc. 20 mhz channel spacing for all mcs rates mcs 15 ? ?69.0 ? dbm (total) mcs 8 ? ?89.0 ? dbm (total) mcs 7 ? ?74.9 ? dbm/core mcs 6 ? ?76.6 ? dbm/core mcs 5 ? ?78 ? dbm/core mcs 4 ? ?82.4 ? dbm/core mcs 3 ? ?85.5 ? dbm/core mcs 2 ? ?89.3 ? dbm/core mcs 1 ? ?91.2 ? dbm/core mcs 0 ? ?92.5 ? dbm/core siso rx sensitivity (10% per for 4096 octet psdu) defined for default parameters: gf, 800 ns gi, and non- stbc. 40 mhz channel spacing for all mcs rates mcs 7 ? ?69.4 ? dbm mcs 6 ? ?71.1 ? dbm mcs 5 ? ?72.5 ? dbm mcs 4 ? ?77 ? dbm mcs 3 ? ?80 ? dbm mcs 2 ? ?83.8 ? dbm mcs 1 ? ?86 ? dbm mcs 0 ? ?88.1 ? dbm mimo rx sensitivity (10% per for 4096 octet psdu) defined for default parameters: gf, 800 ns gi, and non- stbc. 40 mhz channel spacing for all mcs rates mcs 15 ? ?67.0 ? dbm (total) mcs 8 ? ?86.5 ? dbm (total) mcs 7 ? ?71.9 ? dbm/core mcs 6 ? ?73.7 ? dbm/core mcs 5 ? ?75.1 ? dbm/core mcs 4 ? ?79.6 ? dbm/core mcs 3 ? ?82.7 ? dbm/core mcs 2 ? ?86.5 ? dbm/core mcs 1 ? ?88.6 ? dbm/core mcs 0 ? ?90.4 ? dbm/core input in-band ip3 maximum lna gain ? ?15.5 ? dbm minimum lna gain ? ?1.5 ? dbm maximum receive level @ 5.24 ghz @ 6, 9, 12 mbps ?29.5 ? ? dbm @ 18, 24, 36, 48, 54 mbps ?29.5 ? ? dbm lpf 3 db bandwidth ? 9 ? 18 mhz table 14: wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit wlan 5 ghz receiver performance specifications bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 62 adjacent channel rejection (difference between interfering and desired signal (20 mhz apart) at 10% per for 1000 octet psdu with desired signal level as specified in condition/notes) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db 65 mbps ofdm ?61 dbm ?2 ? ? db alternate adjacent channel rejection (difference between interfering and desired signal (40 mhz apart) at 10% per for 1000 a octet psdu with desired signal level as specified in condition/notes) 6 mbps ofdm ?78.5 dbm 32 ? ? db 9 mbps ofdm ?77.5 dbm 31 ? ? db 12 mbps ofdm ?75.5 dbm 29 ? ? db 18 mbps ofdm ?73.5 dbm 27 ? ? db 24 mbps ofdm ?70.5 dbm 24 ? ? db 36 mbps ofdm ?66.5 dbm 20 ? ? db 48 mbps ofdm ?62.5 dbm 16 ? ? db 54 mbps ofdm ?61.5 dbm 15 ? ? db 65 mbps ofdm ?60.5 dbm 14 ? ? db maximum receiver gain ??100?db gain control step ? ? 3 ? db rssi accuracy b range ?98 dbm to ?30 dbm ?5 ? 5 db range above ?30 dbm ?8 ? 8 db return loss z o = 50 ? 610?db receiver cascaded noise figure at maximum gain ? 5.0 ? db a. for 65 mbps, the size is 4096. b. the minimum and maximum values shown have a 95% confidence level. table 14: wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit wlan 5 ghz transmitter performance specifications bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 63 wlan 5 ghz transmitter performance specifications note: the specifications in ta b le 1 5 are measured at the chip port, unless otherwise specified. table 15: wlan 5 ghz transmitter performance specifications a a. all power targets are measured at the chip output and were measured using revision 6 reference boards. parameter condition/notes min. typ. max. unit frequency range ? 4900 ? 5845 mhz harmonic level (at ?5 dbm) 9.8?11.570 ghz 2nd harmonic ? tbd ? dbm/ mhz ofdm evm ofdm, 64 qam 0 dbm ? ?30.4 ? db ofdm evm ofdm, 64 qam ?3 dbm ? ?32.7 ? db ofdm evm mcs7 ?6 dbm ? ?33.6 ? db tx power at chip port for highest power level setting at 25c, vdd33 = 3.3v, spectral mask and evm compliance b b. derate by 1.2 db for pa_vdd supply (direct supply to pa) of 3v. ieee 802.11a 6 mbps, siso+cdd, low subband, ? 20.0 ? dbm ieee 802.11a 6 mbps, siso+cdd, mid subband, ? 19.5 ? dbm ieee 802.11a 6 mbps, siso+cdd, high subband, ? 19.0 ? dbm ieee 802.11a 54 mbps @ 25 db evm, siso+cdd, low subband ? 17.5 ? dbm ieee 802.11a 54 mbps @ 25 db evm, siso+cdd, mid subband ? 16.5 ? dbm ieee 802.11a 54 mbps @ 25 db evm, siso+cdd, high subband ? 16.5 ? dbm mcs7 ht20 @ 28 db evm, siso+cdd, low subband ? 16.5 ? dbm mcs7 ht20 @ 28 db evm, siso+cdd, mid subband ? 15.5 ? dbm mcs7 ht20 @ 28 db evm, siso+cdd, high subband ? 15.5 ? dbm mcs7 ht40 @ 28 db evm, siso+cdd, low subband ? 16.5 ? dbm mcs7 ht40 @ 28 db evm, siso+cdd, mid subband ? 15.5 ? dbm mcs7 ht40 @ 28 db evm, siso+cdd, high subband ? 15.5 ? dbm phase noise 37.4 mhz crystal, integrated from 10 khz to 10 mhz ? 0.7 ? degrees tx power control dynamic range ?20??db carrier suppression ? 15 ? ? dbc gain control step ? ? 0.25 ? db return loss z o = 50 ? ?6?db general spurious emissions specifications bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 64 general spurious emissions specifications table 16: general spurious emissions specifications parameter condition/notes min. typ. max. unit frequency range ? tbd tbd tbd mhz general spurious emissions tx emissions 30 mhz < f < 1 ghz rbw = 100 khz tbd tbd tbd dbm 1 ghz < f < 12.75 ghz rbw = 1 mhz tbd tbd tbd dbm 1.8 ghz < f < 1.9 ghz rbw = 1 mhz tbd tbd tbd dbm 5.15 ghz < f < 5.3 ghz rbw = 1 mhz tbd tbd tbd dbm rx/standby emissions 30 mhz < f < 1 ghz rbw = 100 khz tbd tbd tbd dbm 1 ghz < f < 12.75 ghz rbw = 1 mhz tbd tbd tbd dbm 1.8 ghz < f < 1.9 ghz rbw = 1 mhz tbd tbd tbd dbm 5.15 ghz < f < 5.3 ghz rbw = 1 mhz tbd tbd tbd dbm internal regulator electrical specifications bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 65 section 11: internal regulator electrical specifications functional operation is not guaranteed outside of the specification limits provided in this section. core buck switching regulator note: values in this data sheet are design goals and are subject to change based on the results of device characterization. table 17: core buck switching regulator (cbuck) specifications specification notes min. typ. max. units input supply voltage dc voltage range inclusive of disturbances (vbat). 3.0 3.3 5.25 v pwm mode switching frequency forced pwm without fll enabled 2.8 4 5.2 mhz forced pwm with fll enabled 3.6 4 4.4 mhz pwm output current ? ? ? 600 ma output current limit peak inductor current 1100 1400 ? ma output voltage range programmable, 30 mv steps default = 1.35v 1.2 1.35 1.5 v pwm output voltage dc accuracy includes load and line regulation. forced pwm mode ?4 ? 4 % pwm ripple voltage, static measure with 20 mhz bandwidth limit. static load. max. ripple based on vbat = 3.3v, vout = 1.35v, fsw = 4 mhz, 2.2 h inductor l > 1.05 h, cap+board total-esr < 20 m ? , cout > 1.9 f, esl < 200 ph ?720mvpp pwm mode peak efficiency peak efficiency at 200 ma load vout = 1.35v, vbat = 3.3v at 25c, fsw = 4 mhz 2.2 h inductor 0806 with dcr = 0.11 ? 25% and acr <1 ? at 4mhz 78 84 ? % pfm mode efficiency 10 ma load current vout = 1.35v, vbat = 3.3v at 25c, cap+board total-esr < 20 m ? , cout = 4.7 f, esl < 200 ph fll = off 0603-size, l = 2.2 h, dcr = 240 m ? 25%, acr < 2 ? 67 77 ? % core buck switching regulator bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 66 lpom efficiency 1 ma load current, vout = 1.35v, vbat = 3.3v at 25c, cap+board total-esr < 20 m ? , cout = 4.7 f, esl<200ph fll=off l=2.2 h, dcr = 240 m ? 25%, acr < 2 ? 55 65 ? % start-up time from power down vddio already on and steady. time from reg_on rising edge to cldo reaching 1.2v ? 674 850 s external inductor 0806 with dcr = 0.11 ? 25% and acr <1 ? ?2.2?h external output capacitor ceramic, x5r, 0402, esr <30 m ? at 4 mhz, 20%, 6.3v 2 a 4.7 ? f external input capacitor for sr_vddbatp5v pin, ceramic, x5r, 0603, esr < 30 m ? at 4 mhz, 20%, 6.3v, 4.7 f 0.67 a 4.7 ? f input supply voltage ramp-up time 0 to 4.3v 40 ? ? s a. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. table 17: core buck switching regulator (cbuck) specifications (cont.) specification notes min. typ. max. units cldo bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 67 cldo table 18: cldo specifications specification notes min. typ. max. units input supply voltage, v in min. v in = v o + 0.15v = 1.35v (for vo = 1.2v) dropout voltage requirement must be met under maximum load. 1.2 1.35 1.5 v output current ? 0.2 ? 300 ma output voltage, v o programmable in 25 mv steps. default = 1.2.v 1.1 1.2 1.275 v dropout voltage at max load ? ? 150 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ? 20 a max. load ? 2100 ? a line regulation v in from (v o + 0.15v) to 1.5v, maximum load ? ? 5 mv/v load regulation load from 1 ma to 300 ma; v in (v o + 0.15v) ? 0.025 0.045 mv/ma psrr @1 khz, vin v o + 0.15v, c o = 4.7 f 20 ? db start-up time of pmu vddio up and steady. time from the reg_on rising edge to the cldo reaching 99% of v o ? 550 850 s ldo turn-on time ldo turn-on time when rest of the chip is up ? ? 180 s external output capacitor, c o to ta l e s r : 5 m ? ?240 m ? 1.32 a a. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 4.7 ? f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. ?12.2f lnldo1 bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 68 lnldo1 table 19: lnldo1 specifications specification notes min. typ. max. units input supply voltage , vin min. v in = v o +0.15v = 1.35v (for v o = 1.2v) dropout voltage requirement must be met under maximum load. 1.2 1.35 1.5 v output current ? 0.2 ? 325 ma output voltage, v o programmable in 25 mv steps. default = 1.2v 1.1 1.2 1.275 v dropout voltage at maximum load ? ? 150 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ? 88 ? a max. load ? 2100 ? a line regulation v in from (v o + 0.15v) to 1.5v, 300 ma load ? ? +5 mv/v load regulation load from 1 ma to 300 ma; v in (v o + 0.15v) ? 0.025 0.045 mv/ma output noise @30 khz, 60?325 ma load c o = 4.7 f @100 khz, 60?325 ma load c o = 4.7 f ? ? 60 30 nv/rt hz nv/rt hz psrr @ 1khz, input > 1.35v, c o = 4.7 f, v o = 1.2v 20 ? ? db start-up time of pmu vddio up and steady. time from reg_on rise edge to lnldo1 reaching 99% of v o ? 550 850 s ldo turn-on time ldo turn-on time when rest of chip is up ? ? 180 s external output capacitor, c o total esr (trace/capacitor): 5 m ? ?240 m ? 1.32 a a. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 4.7 ? f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. ? 1 2.2 f lnldo2 bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 69 lnldo2 table 20: lnldo2 specifications specification notes min. typ. max. units input supply voltage, vin min. vin = v o + 0.15v = 1.35v (for v o = 1.2v) dropout voltage requirement must be met under maximum load. 1.2 1.35 1.5 v output current ? ? ? 150 ma output voltage, v o programmable in 25 mv steps. default = 1.2v 1.1 1.2 1.275 v dropout voltage at maximum load ? ? 150 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ? 44 ? a max. load ? 970 990 a line regulation v in from (v o + 0.15v) to 1.5v, max load ? ? 5.5 mv/v load regulation load from 1 ma to 150 ma; v in (v o + 0.15v) ? 0.025 0.045 mv/ma output noise @30 khz, 60-150 ma load c o = 2.2 f @100 khz, 60-150 ma load c o = 2.2 f ? ? 60 35 nv/rt hz nv/rt hz psrr @ 1khz, input > 1.35v, c o = 2.2 f, v o = 1.2v 20 ? ? db ldo turn-on time ldo turn-on time when rest of chip is up ? ? 180 s external output capacitor, c o total esr (trace/capacitor): 5 m ? ?240 m ? 0.5 a a. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 2.2 4.7 f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. ? 1 2.2 f system power consumption bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 70 section 12: system power consumption wlan current consumption wlan current consumption measurements are shown in ta b le 2 1 and table 22 on page 71 . note: ? values in this data sheet are design goals and are subject to change based on the results of device characterization. ? unless otherwise stated, these values apply for the conditions specified in table 10: ?recommended operating conditions and dc characteristics,? on page 54 . table 21: 2.4 ghz wlan current consumption parameter vdd33 = 3.3v vddio = 3.3v unit current pm1 dtim1 20 23.6 ma current pm1 dtim3 17.8 23.6 ma off current 0.13 0.02 ma sleep (interbeacon sleep) 16.2 23.6 ma listen current 100 23.7 ma continuous rx mode @ 54 mbps 102 23.7 ma continuous rx mode @ mcs7 ht20 102 23.8 ma continuous rx mode @ mcs8 ht20 103 23.8 ma continuous rx mode @ mcs15 ht20 109 23.8 ma 802.11b 1 mbps @ 19.0 dbm 354 23.7 ma 802.11g 6 mbps @ 22.5 dbm 464 23.7 ma 802.11g 54 mbps, siso, evm = ?25 dbc @ 18.5 dbm 348 23.7 ma 802.11g 54 mbps, cdd, evm = ?25 dbc @ 18.5 dbm 677 23.7 ma mcs7 ht20, siso, evm = ?28 dbc @ +17.0 dbm 325 23.7 ma mcs7 ht20, cdd, evm = ?28 dbc @ +17.0 dbm 615 23.7 ma mcs7 ht40, siso, evm = ?28 dbc @ +17.0 dbm 362 23.7 ma mcs7 ht40, cdd, evm = ?28 dbc @ +17.0 dbm 670 23.7 ma mcs15 ht20, evm = ?28 dbc @ +17.0 dbm/core 625 23.7 ma mcs15 ht40, evm = ?28 dbc @ +17.0 dbm/core 674 23.7 ma wlan current consumption bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 71 table 22: 5 ghz wlan current consumption parameter vdd33 = 3.3v vddio = 3.3v unit current pm1 dtim1 20.1 23.6 ma current pm1 dtim1 17.4 23.6 ma off current 0.13 0.02 ma sleep (interbeacon sleep) 16.1 23.6 ma continuous rx mode 6 mbps 110 23.8 ma continuous rx mode 54 mbps 109 23.8 ma continuous rx mode mcs7 ht20 110 23.8 ma continuous rx mode mcs7 ht40 152 23.8 ma continuous rx mode mcs8 ht20 123 23.8 ma continuous rx mode mcs8 ht40 154 23.8 ma continuous rx mode mcs15 ht20 116 23.8 ma continuous rx mode mcs15 ht40 171 23.8 ma 802.11a 6 mbps, siso @ +19.5 dbm 367 23.8 ma 802.11a 6 mbps, cdd, @ +19.5 dbm 710 23.8 ma 802.11a 54 mbps, siso @ +16.5 dbm 326 23.8 ma 802.11a 54 mbps, cdd @ +16.5 dbm 610 23.8 ma mcs7 ht20 @ ?28 dbc evm, siso @ +15.5 dbm 312 23.8 ma mcs7 ht20 @ ?28 dbc evm, cdd,@ +15.5 dbm 580 23.8 ma mcs7 ht40 @ ?28 dbc evm, siso @ +15.5 dbm 346 23.8 ma mcs7 ht40 @ ?28 dbc evm, cdd @ +15.5 dbm 632 23.8 ma mcs15 ht20, ?28 dbc evm @ +15.5 dbm/core 585 23.8 ma mcs15 ht40, ?28 dbc evm @ +15.5 dbm/core 630 23.8 ma interface timing and ac characteristics bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 72 section 13: interface timing and ac characteristics jtag timing table 23: jtag timing characteristics signal name period output maximum output minimum setup hold tck 125 ns ? ? ? ? tdi ? ? ? 20 ns 0 ns tms ? ? ? 20 ns 0 ns tdo ? 100 ns 0 ns ? ? jtag_trst 250 ns ? ? ? ? power-up sequence and timing bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 73 section 14: power-up sequence and timing sequencing of reset and regulator control signals the bcm43243 has signals that allow the host to control power consumption by enabling or disabling the wlan and internal regulator blocks. these signals are described below. additionally, diagrams are provided to indicate proper sequencing of the signals for various operational states (see figure 17 and figure 18 ). the timing values indicated are minimum required values; longer delays are also acceptable. control signal and timing the wl_reg_on control signal is used by the pmu to power up the wlan section. when this pin is high, the regulators are enabled and the wlan section is out of reset. when this pin is low, the wlan section is in reset. if wl_reg_on is low, the regulators are disabled. figure 17: wlan = on figure 18: wlan = off note: the bcm43243 has an internal power-on reset (por) circuit. the device will be held in reset for a maximum of 110 ms after vddc and vddio have both passed the 0.6v threshold. wait at least 150 ms after vddc and vddio are available before initiating sdio accesses. 32.678 khz sleep clock vbat vddio wl_reg_on 90% of vh ~ 2 sleep cycles 32.678 khz sleep clock vbat vddio wl_reg_on package information bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 74 section 15: package information package thermal characteristics junction temperature estimation and psi jt versus theta jc package thermal characterization parameter psi?j t ( jt ) yields a better estimation of actual junction temperature (t j ) versus using the junction-to-case thermal resistance parameter theta?j c ( jc ). the reason for this is that jc assumes that all the power is dissipated through the top surface of the package case. in actual applications, some of the power is dissipated through the bottom and sides of the package. ? jt takes into account power dissipated through the top, bottom, and sides of the package. the equation for calculating the device junction temperature is: t j = t t + p x jt where: ?t j = junction temperature at steady-state condition (c) ?t t = package case top center temperature at steady-state condition (c) ? p = device power dissipation (watts) ? jt = package thermal characteristics; no airflow (c/w) environmental characteristics for environmental characteristics data, see table 8: ?environmental ratings,? on page 53 . table 24: package jedec thermal characteristics characteristic fcfbga ja (c/w) (value in still air) 33.65 jb (c/w) 11.38 jc (c/w) 15.52 jt (c/w) 8.82 jb (c/w) 13.93 maximum junction temperature t j a (c) a. absolute junction temperature limits are maintained through active thermal monitoring and dynamic tx duty cycle limiting. 125 maximum power dissipation (w) 2.1 mechanical information bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 75 section 16: mechanical information figure 19: fcfbga package mechanical information ordering information bcm43243 preliminary data sheet broadcom confidential broadcom ? single-chip mac/baseband/radio april 16, 2015 ? 43243-ds100-r page 76 section 17: ordering information part number package operating ambient temperature BCM43243KFFBG fcfbga (10.00 mm x 10.00 mm, 0.4 mm pitch) ?10c to +70c a a. absolute junction temperature limits are maintained through active thermal monitoring and dynamic tx duty cycle limiting. phone: 949-926-5000 fax: 949-926-5203 e-mail: info@broadcom.com web: www.broadcom.com broadcom corporation 5300 california avenue irvine, ca 92617 ? 2015 by broadcom corporation. all rights reserved. 43243-ds100-r april 16, 2015 broadcom ? corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. information furnished by broadcom corporation is believed to be accurate and reliable. however, broadcom corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. bcm43243 preliminary data sheet ? |
Price & Availability of BCM43243KFFBG
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |